- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C7100BNA PCI Bus Interface/Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁(yè)數(shù)： | 24/118頁(yè) |
| 文件大?。?/td> | 2962K |
| 代理商： | PI7C7100BNA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)
16
05/08/00
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read
transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read
transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the
initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator
terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes
first. When the buffer empties, PI7C7100 reflects the stalled condition to the initiator by de-asserting TRDY# until more
read data is available; otherwise, PI7C7100 does not insert any target wait states. When the initiator terminates the
transaction, PI7C7100 de-assertion of FRAME# on the initiator bus is forwarded to the target bus. Any remaining read data
is discarded.
PI7C7100 implements a discard timer that starts counting when the delayed read completion is at the head of the delayed
transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable
through configuration register. If the initiator does not repeat the read transaction and before the discard timer expires,
PI7C7100 discards the read transaction and read data from its queues. PI7C7100 also conditionally asserts P_SERR#
(see Section 7.4).
PI7C7100 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator
starts a read transaction that matches the address and read command of a read transaction that is already queued, the
current read command is not posted as it is already contained in the delayed transaction queue.
See Section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7100.
4.7 Configuration Transactions
Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed
by configuration commands. All registers are accessible in configuration space only.
In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C7100 also
forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle
generation.
To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1.
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type
0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b.
Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle
is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and
the lowest two address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register
to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of
a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type
1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI
bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction
is targeted. For timing diagrams, see Figures 1-8 in Appendix A.
4.7.1 Type 0 Access to PI7C7100
The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration
space cannot be accessed from the secondary bus. The PI7C7100 responds to a Type 0 configuration transaction by
asserting P_DEVSEL# when the following conditions are met during the address phase:
The bus command is a configuration read or configuration write transaction.
Lowest two address bits P_AD[1:0] must be 00b.
Signal P_IDSEL must be asserted.
Function code is either 0 for configuration space of S1, or 1 for configuration space of S2 as PI7C7100 is a multi-function
device.
PI7C7100 limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data
transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects,
all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。