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05/08/00
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PI7C7100
ADVANCE INFORMATION
1.
2.
3.
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
4.
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.8
4.8.1
4.8.2
4.8.3
4.8.4
Introduction/Product Features
...............................................................................................................................1
PI7C7100 Block Diagram
......................................................................................................................................3
Signal Definitions
...................................................................................................................................................4
Signal Types ............................................................................................................................................................4
Signals ......................................................................................................................................................................4
Primary Bus Interface Signals ..................................................................................................................................4
Secondary Bus Interface Signals .............................................................................................................................6
Clock Signals............................................................................................................................................................8
Miscellaneous Signals .............................................................................................................................................8
JTAG Boundary Scan Signals..................................................................................................................................9
Power and Ground....................................................................................................................................................9
PCI Bus Operation
................................................................................................................................................ 10
Types of Transactions ........................................................................................................................................... 10
Single Address Phase ............................................................................................................................................11
Device Select (DEVSEL#) Generation ....................................................................................................................11
Data Phase ............................................................................................................................................................. 11
Write Transactions ................................................................................................................................................ 11
Posted Write Transactions .................................................................................................................................... 11
Memory Write and Invalidate Transactions.......................................................................................................... 12
Delayed Write Transactions .................................................................................................................................. 12
Write Transaction Address Boundaries ................................................................................................................ 13
Buffering Multiple Write Transactions.................................................................................................................. 13
Fast Back-to-Back Write Transactions .................................................................................................................. 13
Read Transactions ................................................................................................................................................. 14
Prefetchable Read Transactions ............................................................................................................................ 14
Non-prefetchable Read Transactions ....................................................................................................................14
Read Pre-fetch Address Boundaries...................................................................................................................... 14
Delayed Read Requests ......................................................................................................................................... 15
Delayed Read Completion with Target .................................................................................................................. 15
Delayed Read Completion on Initiator Bus ........................................................................................................... 15
Configuration Transactions ................................................................................................................................... 16
Type 0 Access to PI7C7100 ................................................................................................................................... 16
Type 1 to Type 0 Conversion ................................................................................................................................17
Type 1 to Type 1 Forwarding ................................................................................................................................18
Special Cycles ........................................................................................................................................................19
Transaction Termination ........................................................................................................................................ 19
Master Termination Initiated by PI7C7100 ............................................................................................................ 20
Master Abort Received by PI7C7100..................................................................................................................... 20
Target Termination Received by PI7C7100 ............................................................................................................ 21
Target Termination Initiated by PI7C7100 ............................................................................................................. 23
Table of Contents