- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C7100BNA PCI Bus Interface/Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁(yè)數(shù)： | 34/118頁(yè) |
| 文件大?。?/td> | 2962K |
| 代理商： | PI7C7100BNA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)當(dāng)前第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)
26
05/08/00
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded
downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this
range are forwarded upstream from the secondary PCI bus to the primary PCI bus.
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When
the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded
downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O
range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at
address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as
1h to indicate that PI7C7100 supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which
naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at
configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or
chip reset, the value of the I/O base address is initialized to 0000 0000h.
The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits
of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O
addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address
to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset
32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value
of the I/O limit address is reset to 0000 0FFFh.
Note:
The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh,
which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable
bit or the master enable bit in the command register in configuration space.
5.2.2 ISA Mode
PI7C7100 supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode
modifies the response of PI7C7100 inside the I/O address range in order to support mapping of I/O space in the presence
of an ISA bus in the system. This bit only affects the response of PI7C7100 when the transaction falls inside the address
range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of
I/O space (address bits [31:16] are 0000h).
When the ISA enable bit is set, PI7C7100 does not forward downstream any I/O transactions addressing the top 768 bytes
of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the
base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are
forwarded as defined by the address range defined by the I/O base and limit registers.
Accordingly, if the ISA enable bit is set, PI7C7100 forwards upstream those I/O transactions addressing the top 768 bytes
of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register
must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded
upstream only if they fall outside the I/O address range.
When the ISA enable bit is set, devices downstream of PI7C7100 can have I/O space mapped into the first 256 bytes of
each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary.
5.3 Memory Address Decoding
PI7C7100 has three mechanisms for defining memory address ranges for forwarding of memory transactions:
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
This section describes the first two mechanisms. Section 5.4.1 describes VGA mode.
To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register
in configuration space. To enable upstream forwarding of memory transactions, the master-enable bit must be set in
the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。