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參數(shù)資料
| 型號(hào)： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁(yè)數(shù)： | 67/118頁(yè) |
| 文件大?。?/td> | 2962K |
| 代理商： | PI7C7100BNA |
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PI7C7100
ADVANCE INFORMATION
13.2.22 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h)
This register defines the base address of the memory-mapped address range for forwarding the cycle through the
bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The twelve bits are reset to 000h.
The lower 20 address bits (19:0) are assumed to be 00000h.
13.2.23 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h)
This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through
the bridge. Upper twelve bits corresponding to address bit [31:20] are read/write. Upper twelve bits are reset to 0000h.
Lower 20 address bits (19:0) are assumed to be FFFFFh.
13.2.24 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h)
This register defines the base address of the prefetchable memory-mapped address range for forwarding the cycle
through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve
bits are reset to 000h. The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are as-
sumed to be 00000h.
13.2.25 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h)
This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through
the bridge. The upper twelve bits correspond to address bit [31:20] are read/write. The upper twelve bits are reset to 000h.
The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are assumed to be FFFFFh.
13.2.26 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register
(read/write, bit 15-0; offset 30h)
This register defines the upper 16 bits of a 32-bit base I/O address range used for forwarding the cycle through
the bridge.
Reset to 0000h.
13.2.27 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register
(read/write, bit 31-16; offset 30h)
This register defines the upper 16 bits of a 32-bit limit I/O address range used for forwarding the cycle through
the bridge.
Reset to 0000h.
13.2.28 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h)
A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h.
13.2.29 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h)
A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h.
13.2.30 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch)
The register reads as 00h to indicate that PI7C7100 does not use any interrupt pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
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