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參數(shù)資料
| 型號： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁數(shù)： | 50/118頁 |
| 文件大?。?/td> | 2962K |
| 代理商： | PI7C7100BNA |
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7.4 System Error (SERR#) Reporting
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
PI7C7100 uses the P_SERR# signal to report conditionally a number of system error conditions in addition to the special
case parity error conditions described in Section 7.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following conditions apply:
For PI7C7100 to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register.
Whenever PI7C7100 asserts P_SERR#, PI7C7100 must also set the signaled system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7100 asserts P_SERR# when it detects the
secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is set in the bridge control register. In
addition, PI7C7100 also sets the received system error bit in the secondary status register.
PI7C7100 also conditionally asserts P_SERR# for any of the following reasons:
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
24
(default) attempts to deliver (2
24
target re3es received)
Parity error reported on target bus during posted write transaction (see previous section)
Delayed write data discarded after 2
24
(default) attempts to deliver (2
24
target re3es received)
Delayed read data cannot be transferred from target after 2
24
(default) attempts (2
24
target re3es received)
Master timeout on delayed transaction
The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#.
Most of these events have additional device-specific disable bits in the P_SERR# event disable register that make it
possible to mask out P_SERR# assertion for specific events. The master timeout condition has a SERR# enable bit for
that event in the bridge control register and therefore does not have a device-specific disable bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
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