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參數(shù)資料
| 型號： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁數(shù)： | 7/118頁 |
| 文件大?。?/td> | 2962K |
| 代理商： | PI7C7100BNA |
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05/08/00
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PI7C7100
ADVANCE INFORMATION
List of Figures
1-1.
1-2.
1-3.
2-1.
9-1.
15-1. Test Access Port Block Diagram ............................................................................................................................... 69
17-1. 256-Pin PBGA Package Drawing................................................................................................................................74
PI7C7100 on the System Board....................................................................................................................................2
PI7C7100 in Redundant Applications..........................................................................................................................2
PI7C7100 on Network Switching Hub..........................................................................................................................2
PI7C7100 Block Diagram ..............................................................................................................................................3
Secondary Arbiter Example ....................................................................................................................................... 45
List of Tables
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
6-1.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
15-1. TAP Pins ....................................................................................................................................................................70
15-2. JTAG Boundary Register Order ................................................................................................................................72
PCI Transaction ......................................................................................................................................................... 10
Write Transaction Forwarding .................................................................................................................................. 11
Write Transaction Disconnect Address Boundaries ................................................................................................ 13
Read Pre-fetch Address Boundaries ......................................................................................................................... 14
Read Transaction Pre-fetching .................................................................................................................................. 15
Device Number to IDSEL S1_AD or S2_AD Pin Mapping ....................................................................................... 18
Posted Write Target Termination Response ............................................................................................................. 21
Responses to Posted Write Target Termination ....................................................................................................... 22
Responses to Delayed Read Target Termination...................................................................................................... 22
Summary of Tranaction Ordering .............................................................................................................................. 30
Setting the Primary Interface Detected Parity Error Bit ............................................................................................. 36
Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 37
Setting the Primary Interface Data Parity Detected Bit.............................................................................................. 37
Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 38
Assertion of P_PERR#............................................................................................................................................... 39
Assertion of S_PERR#............................................................................................................................................... 40
Assertion of P_SERR# for Data Parity Errors ........................................................................................................... 41
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
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