參數(shù)資料
型號(hào)： PI7C7100BNA
英文描述： PCI Bus Interface/Controller
中文描述： PCI總線接口/控制器
文件頁(yè)數(shù)： 6/118頁(yè)
文件大?。?/td> 2962K
代理商： PI7C7100BNA
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vi
05/08/00
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PI7C7100
ADVANCE INFORMATION
13.2.51 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch).................... 66
13.2.52 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h) ....................... 66
13.2.53 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h)....................... 66
13.2.54 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h) ............... 66
13.2.55 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch).............. 66
14.
Bridge Behavior
.................................................................................................................................................... 67
14.1
Bridge Actions for Various Cycle Types ............................................................................................................... 67
14.2
Transaction Ordering ............................................................................................................................................. 67
14.3
Abnormal Termination (Initiated by Bridge Master) ............................................................................................. 68
14.3.1
Master Abort ......................................................................................................................................................... 68
14.3.2
Parity and Error Reporting ..................................................................................................................................... 68
14.3.3
Reporting Parity Errors........................................................................................................................................... 68
14.3.4
Secondary IDSEL mapping .................................................................................................................................... 68
15.
IEEE 1149.1 Compatible JTAG Controller
........................................................................................................... 69
15.1
Boundary Scan Architecture ................................................................................................................................. 69
15.1.1
TAP Pins ................................................................................................................................................................ 69
15.1.2
Instruction Register ............................................................................................................................................... 69
15.2
Boundary Scan Instruction Set.............................................................................................................................. 70
15.3
TAP Test Data Registers ....................................................................................................................................... 70
15.4
Bypass Register ..................................................................................................................................................... 71
15.5
Boundary-Scan Register......................................................................................................................................... 71
15.6
TAP Controller ....................................................................................................................................................... 71
16.
Electrical and Timing Specifications
.................................................................................................................... 76
16.1
Maximum Ratings................................................................................................................................................... 76
16.2
3.3V DC Specifications ........................................................................................................................................... 76
16.3
3.3V AC Specifications........................................................................................................................................... 77
16.4
Primary and Secondary buses at 33 MHz clock timing .......................................................................................... 77
17.
256-Pin PBGA Package........................................................................................................................................... 78
17.1
Part Number Ordering Information........................................................................................................................ 78
相關(guān)PDF資料
PDF描述
PI7C7100 3-Port PCI Bridge
PI7C7100CNA 3-Port PCI Bridge
PI7C7300 3-PORT PCI-to-PCI BRIDGE
PI7C7300A 3-PORT PCI-to-PCI BRIDGE
PI7C7300ANA 3-PORT PCI-to-PCI BRIDGE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7100CNA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge
PI7C7300 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE
PI7C7300A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE
PI7C7300AEVB-3 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C7300ANA 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
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