參數(shù)資料
型號: PCA5007H
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機基帶控制器
文件頁數(shù): 99/112頁
文件大小: 604K
代理商: PCA5007H
1998 Oct 07
99
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 65
Entering the parallel programming mode; note 1
Note
1.
Z = pin is output.
PINS PSEN, ALE AND
EA
RESETIN
RESOUT
PORT 0
DESCRIPTION
000
000
000
1
0
0
0
0
XX
XX
XX
reset
259 or more slow clocks at XTL1
prepare parallel programming mode, enter
external access mode, now clocks must be
provided on TCLK
LJMP 3000H
force P2 to 30H
0
1
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
02
30
00
00
75
87
01
01
XX
discard fetch cycle
MOV PCON, 01H
make microcontroller idle
discard fetch cycle
parallel programming mode active
width
MGR165
ALE
PSEN
variable
execute time
DATA input
AL
driven
DATA input
AH driven
AH driven
P0
P2
3T
4T
5T
6T
0T
1T
2T
3T
4T
5T
6T
....
nT
s
s
ALE, PSEN cycle
tCE
T
instruction execution cycle
Fig.62 External access timing for programming mode entry.
T is the half period of the clock
signal supplied to TCLK.
The minimum duration of one
cycle is 6T. It can be extended by
increments of [0 to n]T if the
execution of an instruction needs
more time (dependant of V
DD
, T,
temperature, opcode).
Execution of an opcode goes in
parallel with the external access
cycle for the next sequential byte.
Eventually an already fetched
byte is discarded depending on
the executed instruction (e.g. any
jump or return).
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