參數(shù)資料
型號(hào)： PCA5007H
廠商： NXP Semiconductors N.V.
英文描述： Pager baseband controller
中文描述： 傳呼機(jī)基帶控制器
文件頁(yè)數(shù)： 30/112頁(yè)
文件大小： 604K
代理商： PCA5007H
1998 Oct 07
30
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
6.11.2
C
LOCK
C
ORRECTION
C
ONTROL
R
EGISTER
(CCON)
The CCON special function register is used to control the clock correction by software.
Table 20
Clock Correction Control Register (CCON, SFR address FCH)
Table 21
Description of the CCON bits
6.11.3
C
LOCK
C
ORRECTION
I
NTERVAL
R
EGISTERS
(CC0
AND
CC1)
The CC0 and CC1 special function registers (together with CCON.3 and CCON.4) are used to define the interval between
subsequent clock correction actions.
Table 22
Clock Correction Interval Register (CC0, SFR address FDH)
Table 23
Clock Correction Interval Register (CC1, SFR address FEH)
7
6
5
4
3
2
1
0
ENB
PLUS
TEST
CIV17
CIV16
BYPASS
SET
BIT
SYMBOL
FUNCTION
CCON.7
ENB
Enable clock correction
. If ENB = 1 has been set, then correction is enabled and will
stay enabled even when the DC/DC converter is shut down and restarted.
±
sign for value
. If PLUS = 1 then clock pulses are inserted, or else deleted.
Test signal
, must always be logic 0 in normal mode. It is s used during test to bypass
the first 9 FFs in the timing generator divider chain. If TEST = 1 the clock rate of the
signals 9600 Hz and 256 Hz is doubled and the frequency on 16 Hz and 4 Hz is
multiplied by 300.
bit 17 of interval value, is used as extension of CC0 and CC1
bit 16 of interval value, is used as extension of CC0 and CC1
unused.
Test signal
, must always be logic 0 in normal mode. It is used during test to generate
76.8 kHz on all outputs of the timing generator (4 Hz, 16 Hz, 256 Hz and 9600 Hz).
A load signal to the interval register
. After a logic 0 to logic 1 transition of this bit the
value of ENB, PLUS, TEST, BYPASS and CIV are copied into the local latches with the
next 76.8 kHz clock pulse. The duration of one MOV instruction is long enough for the
set operation to complete. The SFR values must remain stable for at least one oscillator
period because the actual transfer happens synchronized with the local clock
(see Figs 14 and 16).
CCON.6
CCON.5
PLUS
TEST
CCON.4
CCON.3
CCON.2
CCON.1
CIV17
CIV16
BYPASS
CCON.0
SET
7
6
5
4
3
2
1
0
CIV7
CIV6
CIV5
CIV4
CIV3
CIV2
CIV1
CIV0
7
6
5
4
3
2
1
0
CIV15
CIV14
CIV13
CIV12
CIV11
CIV10
CIV9
CIV8
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