參數(shù)資料
型號: PCA5007H
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機基帶控制器
文件頁數(shù): 82/112頁
文件大?。?/td> 604K
代理商: PCA5007H
1998 Oct 07
82
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Notes
1.
DC/DC converter configured with inductor of L = 470
μ
H, SRL = 5
, input capacitance of C
i
= 4.7
μ
F, ESR = 0.5
,
V
DD
output capacitor C
o
= 4.7
μ
F, ESR = 0.5
, R
BAT
< 1
.
This parameter is not tested during production; it is guaranteed by design.
This parameter depends on external components.
At high load or low battery voltage the inductor charge time can be extended to a full XTL1 period, while the minimum
inductor discharge time remains an
1
2
t
XTL1
period.
The execution time is strongly dependant on command type and addressing mode (see Table 60).
2.
3.
4.
5.
ZIF (I and Q) demodulator
f
offset
S/N
t
(ENA-AVG)
t
ENB
offset from 0 frequency
minimum signal strength
ENA to valid AVG value
ENB to valid demodulator
output
ENB to correct recovered
clock
changing baud rate to
correct recovered clock
note 2
3% bit error rate; note 2
3 kHz offset; note 2
24 samples per symbol;
note 2
note 2
6
95
100
1
kHz
dB(m)
ms
symbol
duration
t
ENC
12/12 positive/negative
transitions of data
2/2 positive/negative
transitions of data
t
BR
note 2
All outputs
t
r,f
rise and fall times for outputs C
L
= 20 pF
15
ns
Open-drain pins SDA and SCL (P1.7 and P1.6)
t
noise
V/
t
noise suppression filter time
slope for the falling edge
60
50
ns
ns/V
R
L
= 20 k
; C
L
= 50 pF;
V
DD
= 2.2 V
R
L
= 20 k
; C
L
= 50 pF
V
DD
= 2.2 V; R
L
= 20 k
;
C
L
= 50 pF
δ
I/
δ
t
I
o(sink)(swL)
slope for both edges
dynamic output sink current
during switching low (Miller
compensated)
250
2
μ
A/ns
mA
OTP programming characteristics
t
SU;VPP
t
W(prog)
t
W(prog)(sec)
t
W(prog)(rec)
V
PP
set-up time
program pulse width
program pulse security bits
program pulse recover time
10
100
200
1
μ
s
μ
s
μ
s
μ
s
AFC-DAC
t
start(DAC)
start-up time disabled DAC
to stable output for code
111111
power supply ripple rejection
(V
DD
-> DAC)
slew time for analog output
from 10 to 90% for a voltage
step of 1 V
note 2
50
100
μ
s
PSRR
0
dB
t
slew
code 010000 <-> 110000
2.5
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP
MAX.
UNIT
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