參數(shù)資料
型號: PCA5007H
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機(jī)基帶控制器
文件頁數(shù): 50/112頁
文件大?。?/td> 604K
代理商: PCA5007H
1998 Oct 07
50
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
4
PS0
UART
Defines the UART interrupt priority level. PS0 = 1 programs it to the higher priority
level.
Defines the I
2
C-bus interrupt priority level. PS1 = 1 programs it to the higher priority
level.
WAKE-UP Defines the WAKE-UP interrupt priority level. PT2 = 1 programs it to the higher
priority level.
/
unused
5
PS1
I
2
C
6
PT2
7
IP1 address F8H: interrupt priority for X2 to X9
(note 2)
0
PX2
P1.0
Defines the EXTERNAL2 interrupt priority level 1. PX2 = 1 programs it to the higher
priority level.
Defines the EXTERNAL3 interrupt priority level 1. PX3 = 1 programs it to the higher
priority level.
Defines the EXTERNAL4 interrupt priority level 1. PX4 = 1 programs it to the higher
priority level.
Defines the SYMBOL interrupt priority level 1. PX5 = 1 programs it to the higher
priority level.
Defines the EXTERNAL6 interrupt priority level 1. PX6 = 1 programs it to the higher
priority level.
Defines the DC/DC CONVERTER interrupt priority level 1. PX7 = 1 programs it to the
higher priority level.
Defines the WATCHDOG interrupt priority level 1. PX8 = 1 programs it to the higher
priority level.
Defines the REAL-TIME CLOCK interrupt priority level 1. PX9 = 1 programs it to the
higher priority level.
1
PX3
P1.1
2
PX4
P1.2
3
PX5
SYMBOL
4
PX6
P1.4
5
PX7
DC/DC
6
PX8
WDI
7
PX9
MIN
TCON address 88H: timer/counter mode control register
0
IT0
P3.2
EXTERNAL0 interrupt type control bit
. Set/cleared by software to specify falling
edge/low level triggered external interrupt.
EXTERNAL0 interrupt flag
. Set by hardware when external Interrupt detected.
Cleared by hardware.
EXTERNAL1 interrupt type control bit
. Set/cleared by software to specify falling
edge/low level triggered external interrupt.
EXTERNAL1 interrupt flag
. Set by hardware when external Interrupt detected.
Cleared by hardware.
Timer 0 run control bit
. Set/cleared by software to turn timer on/off.
Timer 0 overflow flag
. Set by hardware on timer/counter overflow. Cleared by
hardware or software.
Timer 1 run control bit
. Set/cleared by software to turn timer on/off.
Timer 1 overflow flag
. Set by hardware on timer/counter overflow. Cleared by
hardware or software.
1
IE0
P3.2
2
IT1
P3.3
3
IE1
P3.3
4
5
TR0
TF0
TIMER 0
TIMER 0
6
7
TR1
TF1
TIMER 1
TIMER 1
IRQ1 address C0H: interrupt request register for X2 to X9
0
1
IQ2
IQ3
P1.0
P1.1
Interrupt request flag from P1.0.
Interrupt request flag from P1.1.
BITS
CONV.
NAME
SOURCE
NOTES
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