參數(shù)資料
型號(hào)： PC8245
廠商： Atmel Corp.
英文描述： Integrated Processor Family
中文描述： 綜合處理器系列
文件頁(yè)數(shù)： 52/61頁(yè)
文件大?。?/td> 429K
代理商： PC8245
52
PC8245
2171D–HIREL–06/04
The driver names and capability of the pins for the PC8245 and that of the PC8240 vary
slightly. Please refer to the Drive Capability table (for the ODCR register at 0x73) in the
PC8240 Integrated Processor Hardware Specifications and Table 5 on page 24 for
more details.
The programmable PCI output valid and output hold feature controlled by bits in the
power management configuration register 2 (PMCR2) <0x72> has changed slightly in
the PC8245. For the PC8240, three bits, PMCR2[6:4] = PCI_HOLD_DEL, are used to
select one of eight possible PCI output timing configurations. PMCR2[6:5] are software
controllable but initially are set by the reset configuration state of the MCP and CKE sig-
nals, respectively; PMCR2[4] can be changed by software. The default configuration for
PMCR2[6:4] = 0b110 since the MCP and CKE signals have internal pull-up resistors,
but this default configuration does not select 33 or 66 MHz PCI operation output timing
parameters for the PC8240; this choice is made by software. For the PC8245, only 2
bits in the power management configuration register 2 (PMCR2), PMCR2[5:4] =
PCI_HOLD_DEL, control the variable PCI output timing. PMCR2[5:4] are software con-
trollable but initially are set by the inverted reset configuration state of the MCP and CKE
signals, respectively. The default configuration for PMCR2[5:4] = 0b00 since the MCP
and CKE signals have internal pull-up resistors and the values from these signals are
inverted; this default configuration selects 66 MHz PCI operation output timing parame-
ters. There are four programmable PCI output timing configurations on the PC8245, see
Table 10 on page 33 for details.
Voltage sequencing requirements for the PC8245 are similar to those for the PC8240;
however, there are two changes which are applicable for the PC8245. First, there is an
additional requirement for the PC8245 that the non-PCI input voltages (V
IN
) must not be
greater than G
V
DD
or O
V
DD
by more than 0.6V at all times including during power-on
reset (see caution 5 in Table “Recommended Operating Conditions” on page 12). Sec-
ond, for the PC8245, L
V
DD
must not exceed O
V
DD
by more than 3.0V at any time
including during power-on reset (see caution 10 in Table “Recommended Operating
Conditions” on page 12); the allowable separation between L
V
DD
and O
V
DD
is 3.6V for
the PC8240.
There is no LA
V
DD
input voltage supply signal on the PC8245 since the SDRAM clock
delay-locked loop (DLL) has power supplied internally. Signal D17 should be treated as
a no connect for the PC8245.
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