參數(shù)資料
型號: PC8245
廠商: Atmel Corp.
英文描述: Integrated Processor Family
中文描述: 綜合處理器系列
文件頁數(shù): 40/61頁
文件大?。?/td> 429K
代理商: PC8245
40
PC8245
2171D–HIREL–06/04
EPIC Serial Interrupt Mode AC
Timing Specifications
Table 14 provides the EPIC serial interrupt mode AC timing specifications for the
PC8245 at recommended operating conditions (see Table “Recommended Operating
Conditions” on page 12) with G
V
DD
= 3.3V ± 5% and L
V
DD
= 3.3V ± 0.3V.
Notes:
1. See the "MPC8245 Integrated Processor User’s Manual" for a description of the EPIC interrupt control register (EICR)
describing S_CLK frequency programming.
2. S_RST, S_FRAME, and S_INT shown in Figure 22 and Figure 23, depict timing relationships to sys_logic_clk and S_CLK
and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the "MPC8245 Integrated Proces-
sor User’s Manual" for a complete description of the functional relationships between these signals.
3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is
implemented and the DLL is locked. See the "MPC8245 Integrated Processor User’s Manual" for a complete clocking
description.
Figure 22.
EPIC Serial Interrupt Mode Output Timing Diagram
Table 14.
EPIC Serial Interrupt Mode AC Timing Specifications
Number
Characteristics
Min
Max
Unit
Notes
1
S_CLK Frequency
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
(1)
2
S_CLK Duty Cycle
40
60
%
3
S_CLK Output Valid Time
6
ns
4
Output Hold Time
0
ns
5
S_FRAME, S_RST Output Valid
Time
1 sys_logic_clk period + 6
ns
(2)(3)
6
S_INT Input Setup Time to S_CLK
1 sys_logic_clk period + 2
ns
(2)(3)
7
S_INT Inputs Invalid (Hold Time)
to S_CLK
0
ns
(2)
S_CLK
S_RST
VM
VM
VM
S_FRAME
sys_logic_clk
3
VM
VM
VM
VM
4
3
5
4
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