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參數(shù)資料
| 型號(hào)： | PC8245 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 25/61頁 |
| 文件大?。?/td> | 429K |
| 代理商： | PC8245 |
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25
PC8245
2171D–HIREL–06/04
Notes:
1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral
logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section “PLL Configuration” on page 45 for valid PLL_CFG[0:4]
settings and PCI_SYNC_IN frequencies.
2. See Table 16 on page 45 and Table 17 on page 47 for more details on VCO limitations for memory and CPU VCO frequen-
cies of various PLL configurations.
3. There are no available PLL_CFG[0:4] settings which support 133 MHz memory interface operation at 300 MHz CPU and
at 350 MHz operation, since the multipliers do not allow a 300:133 and 350:133 ratio relation. However, running these parts
are slower speeds may produce ratios that will run above 100 MHz. See Table 16 on page 45 for the PLL settings.
Clock AC Specifications
Table 7 provides the Clock AC timing specifications at recommended operating condi-
tions, as defined in Section “Input AC Timing Specifications” on page 31. These
specifications are for the default driver strengths indicated in Table 5 on page 24.
At recommended operating conditions (see Table “Recommended Operating Condi-
tions” on page 12) with L
V
DD
= 3.3V ± 0.3V
Notes:
1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4V.
Table 6.
Operating Frequency
Characteristic
(2)
266 MHz
300 MHz
333 MHz
350 MHz
Unit
V
DD
/A
V
DD
/A
V
DD
2 = 2.0
±
100 mV
V
DD
/A
V
DD
/A
V
DD
2 = 2.0
±
100 mV
Processor Frequency (CPU)
100 – 266
100 – 300
100 – 333
100 – 350
MHz
Memory Bus Frequency
50 – 133
50 – 100
(3)
50 – 133
50 – 100
(3)
MHz
PCI Input Frequency
25 – 66
MHz
Table 7.
Clock AC Timing Specifications
Num
Characteristics and Conditions
Min
Max
Unit
Notes
1a
Frequency of Operation (PCI_SYNC_IN)
25
66
MHz
2, 3
PCI_SYNC_IN Rise and Fall Times
–
2.0
ns
(1)
4
PCI_SYNC_IN Duty Cycle Measured at 1.4V
40
60
%
5a
PCI_SYNC_IN Pulse Width High Measured at 1.4V
6
9
ns
(2)
5b
PCI_SYNC_IN Pulse Width Low Measured at 1.4V
6
9
ns
(2)
7
PCI_SYNC_IN Jitter
–
150
ps
8a
PCI_CLK[0:4] Skew (Pin-to-Pin)
–
250
ps
8b
SDRAM_CLK[0:3] Skew (Pin-to-Pin)
–
190
ps
(3)
10
Internal PLL Relock Time
–
100
μs
(2)(4)(5)
15
DLL Lock Range with DLL_EXTEND = 0 Disabled (Default)
(N x T
CLK
– Tdp(max))
≤
Tloop
≤
(N x T
CLK
– Tdp(min))
ns
(6)
16
DLL Lock Range with DLL_EXTEND = 1 Enabled
((N – 0.5) x T
CLK
– Tdp(max))
≤
Tloop
≤
((N – 0.5) T
CLK
–
Tdp(min))
ns
(6)
17
Frequency of Operation (OSC_IN)
25
66
MHz
19
OSC_IN Rise and Fall Times
–
5
ns
(7)
20
OSC_IN Duty Cycle Measured at 1.4V
40
60
%
21
OSC_IN Frequency Stability
–
100
ppm
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