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參數(shù)資料
| 型號： | PC8245 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 49/61頁 |
| 文件大?。?/td> | 429K |
| 代理商： | PC8245 |
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49
PC8245
2171D–HIREL–06/04
System Design
Information
This section provides electrical and thermal design recommendations for successful
application of the PC8245.
PLL Power Supply Filtering
The A
V
DD
and A
V
DD
2 power signals are provided on the PC8245 to provide power to the
peripheral logic/memory bus PLL and the PC603e processor PLL. To ensure stability of
the internal clocks, the power supplied to the A
V
DD
and A
V
DD
2 input signals should be fil-
tered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLLs. Two
separate circuits similar to the one shown in Figure 29 using surface mount capacitors
with minimum effective series inductance (ESL) is recommended for A
V
DD
and A
V
DD
2
power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High
Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small
capacitors of equal value are recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to
minimize noise coupled from nearby circuits. Routing directly as possible from the
capacitors to the input signal pins with minimal inductance of vias is important.
Figure 29.
PLL Power Supply Filter Circuit
Power Supply Sizing
The power consumption numbers provided in Table 3 on page 22 do not reflect power
from the O
V
DD
and G
V
DD
power supplies which are non-negligible for the PC8245. In typ-
ical application measurements, the O
V
DD
power ranged from 200 to 500 mW and the
G
V
DD
power ranged from 300 to 600 mW. The ranges’ low-end power numbers were
results of the PC8245 performing cache resident integer operations at the slowest fre-
quency combination of 33:66:200 (PCI:Mem:CPU) MHz. The O
V
DD
high end range’s
value resulted from the PC8245 operating at the fastest frequency combination of
66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with
alternating ones and zeros to PCI memory. The G
V
DD
high-end range’s value resulted
from the PC8245 operating at the fastest frequency combination of 66:100:350
(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating
ones and zeros on 64-bit boundaries to local memory.
Decoupling
Recommendations
Due to its dynamic power management feature, the large address and data buses, and
its high operating frequencies, the PC8245 can generate transient power surges and
high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the PC8245 system,
and the PC8245 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each
V
DD
, O
V
DD
, G
V
DD
, and L
V
DD
pin of the PC8245. It is also recommended that these decou-
pling capacitors receive their power from separate
V
DD
, O
V
DD
, G
V
DD
, and GND power
planes in the PCB, utilizing short traces to minimize inductance. These capacitors
should have a value of 0.1 μF. Only ceramic SMT (surface mount technology) capaci-
tors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such
that connections are made along the length of the part.
Vdd
AVdd, AVdd2
2.2 μF
2.2 μF
GND
Low ESL surface mount capacitors
10 k
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