參數(shù)資料
型號: PC8245
廠商: Atmel Corp.
英文描述: Integrated Processor Family
中文描述: 綜合處理器系列
文件頁數(shù): 38/61頁
文件大小: 429K
代理商: PC8245
38
PC8245
2171D–HIREL–06/04
Table 13 provides the I
2
C interface output AC timing specifications for the PC8245 at recommended operating conditions
(see Table “Recommended Operating Conditions” on page 12) with L
V
DD
= 3.3V
±
0.3V.
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency divider
register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and
SDA are delayed signals from what is seen in real time on the
I
2
C interface
bus. The qualified SCL, SDA signals are
delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is added to
the value in the table (where this note is referenced). See Figure 19.
3. D
FDR
is the decimal divider number indexed by FDR[5:0] value. Refer to Table 10-5 in the "MPC8245 Integrated Processor
User’s Manual". FDR[x] refers to the frequency divider register I2CFDR bit x. N is equal to a variable number that would
make the result of the divide (data hold time value) equal to a number less than 16. M is equal to a variable number that
would make the result of the divide (data hold time value) equal to a number less than 9.
4. Since SCL and SDA are open-drain type outputs, which the PC8245 can only drive low, the time required for SCL or SDA to
reach a high level depends on external signal capacitance and pull-up resistor values.
5. Specified at a nominal 50 pF load.
Figure 18.
I
2
C Interface Timing Diagram I
Table 13.
I
2
C Interface Output AC Timing Specifications
Number
Characteristics
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0) x (D
FDR
/16)/2N +
(FDR[5] == 1) x (D
FDR
/16)/2M
CLKs
(1)(2)(3)
2
Clock low period
D
FDR
/2
CLKs
(1)(2)(3)
3
SCL/SDA rise time (from 0.5V to 2.4V)
ms
(4)
4
Data hold time
8.0 + (16 x 2
FDR[4:2]
) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
CLKs
(1)(2)(3)
5
SCL/SDA fall time (from 2.4V to 0.5V)
< 5
ns
(5)
6
Clock high time
D
FDR
/2
CLKs
(1)(2)(3)
7
Data setup time (PC8245 as a master only)
(D
FDR
/2) – (Output data hold time)
CLKs
(1)(3)
8
Start condition setup time (for repeated start
condition only)
D
FDR
+ (Output start condition hold
time)
CLKs
(1)(2)(3)
9
Stop condition setup time
4.0
CLKs
(1)(2)
SCL
SDA
VM
VM
6
2
1
4
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