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參數(shù)資料
| 型號： | PC8245 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 50/61頁 |
| 文件大?。?/td> | 429K |
| 代理商： | PC8245 |
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50
PC8245
2171D–HIREL–06/04
In addition, it is recommended that there be several bulk storage capacitors distributed
around the PCB, feeding the
V
DD
, O
V
DD
, G
V
DD
, and L
V
DD
planes, to enable quick recharg-
ing of the smaller chip capacitors. These bulk capacitors should have a low ESR
(equivalent series resistance) rating to ensure the quick response time necessary. They
should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100 – 330 μF (AVX TPS tantalum or Sanyo
OSCON).
Connection
Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an
appropriate signal level. Unused active-low inputs should be tied to O
V
DD
. Unused
active-high inputs should be connected to GND. All NC (no connect) signals must
remain unconnected.
Power and ground connections must be made to all external
V
DD
, O
V
DD
, G
V
DD
, L
V
DD
, and
GND pins of the PC8245.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and
then returned to the PCI_SYNC_IN input of the PC8245.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM
devices and then returned to the SDRAM_SYNC_IN input of the PC8245. The trace
length may be used to skew or adjust the timing window as needed. See Motorola appli-
cation notes AN1849/D and AN2164/D for more information on this topic. Note that
there is an SDRAM_SYNC_IN to PCI_SYNC_IN time requirement. (See Table 9 on
page 31.)
Pull-up/Pull-down Resistor
Requirements
The data bus input receivers are normally turned off when no read operation is in
progress; therefore, they do not require pull-up resistors on the bus. The data bus sig-
nals are: MDH[0:31], MDL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity
bits (MDL[0:31] and PAR[4:7]) will be disabled, and their outputs will drive logic zeros
when they would otherwise normally be driven. For this mode, these pins do not require
pull-up resistors and should be left unconnected by the system to minimize possible out-
put switching.
The TEST0 pin requires a pull-up resistor of 120
or less connected to O
V
DD
.
It is recommended that RTC have weak pull-up resistors (2 k
– 10 k
) connected to
G
V
DD
_O
V
DD
.
It is recommended that the following signals be pulled up to O
V
DD
with weak pull-up
resistors (2 k
– 10 k
): SDA, SCL, SMI, SRESET/SDMA12, TBEN/SDMA13,
CHKSTOP_IN/SDMA14, TRIG_IN/RCS2, and DRDY.
It is recommended that the following PCI control signals be pulled up to L
V
DD
with weak
pull-up resistors (2 k
– 10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP,
and TRDY. The resistor values may need to be adjusted stronger to reduce induced
noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0],
REQ4/DA4, TCK, TDI, TMS, and TRST. See Table 1 on page 6 for more information.
The following pins have internal pull-up resistors enabled only while device is in the
reset state:
GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2],
PMAA[0:2], and QACK/DA0. See Table 1 on page 6 for more information.
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