參數(shù)資料
型號(hào)： PC8245
廠商： Atmel Corp.
英文描述： Integrated Processor Family
中文描述： 綜合處理器系列
文件頁(yè)數(shù)： 4/61頁(yè)
文件大?。?/td> 429K
代理商： PC8245
4
PC8245
2171D–HIREL–06/04
Peripheral logic
Peripheral Logic Bus
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Supports various operating frequencies and bus divider ratios
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32-bit address bus, 64-bit data bus
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Supports full memory coherency
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Decoupled address and data buses for pipelining of peripheral logic bus
accesses
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Store gathering on peripheral logic bus-to-PCI writes
Memory interface
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Supports up to 2 Gbytes of SDRAM memory
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High-bandwidth data bus (32- or 64-bit) to SDRAM
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Programmable timing supporting SDRAM
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Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
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Write buffering for PCI and processor accesses
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Supports normal parity, read-modify-write (RMW), or ECC
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Data-path buffering between memory interface and processor
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Low-voltage TTL logic (LVTTL) interfaces
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272 Mbytes of base and extended ROM/Flash/PortX space
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Base ROM space supports 8-bit data path or same size as the SDRAM data
path (32- or 64-bit)
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Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64-
bit (wide) data path
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PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller
interface with programmable address strobe timing, data ready input signal
(DRDY), and 4 chip selects
32-bit PCI interface
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Operates up to 66 MHz
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PCI 2.2-compliant
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PCI 5.0V tolerance
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Support for dual address cycle (DAC) for 64-bit PCI addressing (master only)
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Support for PCI locked accesses to memory
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Support for accesses to PCI memory, I/O, and configuration spaces
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Selectable big- or little-endian operation
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Store gathering of processor-to-PCI write and PCI-to-memory write
accesses
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Memory prefetching of PCI read accesses
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Selectable hardware-enforced coherency
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PCI bus arbitration unit (five request/grant pairs)
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PCI agent mode capability
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Address translation with two inbound and outbound units (ATU)
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Some internal configuration registers accessible from PCI
Two-channel integrated DMA controller (writes to ROM/PortX not supported)
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