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參數(shù)資料
| 型號(hào)： | PC28F640J3F75A |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, PBGA64 |
| 封裝： | LEAD FREE, BGA-64 |
| 文件頁數(shù)： | 29/66頁 |
| 文件大小： | 740K |
| 代理商： | PC28F640J3F75A |
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March 2010
Datasheet
208032-02
35
Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
9.1.1
Clearing the Status Register
The Status Register (SR) contain Status and error bits which are set by the device. SR
status bits are cleared by the device, however SR error bits are cleared by issuing the
Clear SR command (see Table 21). Resetting the device also clears the SR.
Issuing the Clear SR command places the device in Read SR mode.
Note:
Care should be taken to avoid SR ambiguity. If a command sequence error occurs while
in an Erase Suspend condition, the SR will indicate a Command Sequence error by
setting SR.4 and SR.5. When the erase operation is resumed (and finishes), any errors
that may have occurred during the erase operation will be masked by the Command
Sequence error. To avoid this situation, clear the Status Register prior to resuming a
suspended erase operation. The Clear SR command functions independent of the
voltage level on VPEN.
9.2
Read Operations
Four types of data can be read from the device: array data, device information, CFI
data, and device status. Upon power-up or return from reset, the device defaults to
Read Array mode. To change the device’s read mode, the appropriate command must
be issued to the device. Table 22 shows the command codes used to configure the
device for the desired read mode. The following sections describe each read mode.
9.2.1
Read Array
Upon power-up or return from reset, the device defaults to Read Array mode. Issuing
the Read Array command places the device in Read Array mode. Subsequent reads
output array data on DQ[15:0]. The device remains in Read Array mode until a
different read command is issued, or a program or erase operation is performed, in
which case, the read mode is automatically changed to Read Status.
To change the device to Read Array mode while it is programming or erasing, first issue
the Suspend command. After the operation has been suspended, issue the Read Array
command. When the program or erase operation is subsequently resumed, the device
will automatically revert back to Read Status mode.
Note:
Issuing the Read Array command to the device while it is actively programming or
erasing causes subsequent reads from the device to output invalid data. Valid array
data is output only after the program or erase operation has finished.
Table 21: Clear Status Register Command Bus-Cycles
Command
Setup Write Cycle
Confirm Write Cycle
Address Bus
Data Bus
Address Bus
Data Bus
Clear Status Register
Device Address
0050h
—
Table 22: Read Mode Command Bus-Cycles
Command
Setup Write Cycle
Confirm Write Cycle
Address Bus
Data Bus
Address Bus
Data Bus
Read Array
Device Address
00FFh
—
Read Status Register
Device Address
0070h
—
Read Device Information
Device Address
0090h
—
CFI Query
Device Address
0098h
—
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F640J3F75B | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel |
| PC28F640J3F75B TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 75NS TBGA |
| PC28F640J3F75D | 制造商:Micron Technology Inc 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel 制造商:Micron Technology 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) |
| PC28F640J3F75E | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays |
| PC28F640P30B85 | 制造商:Intel 功能描述:MM#873919 64MB FLASH SOLD->NUM |
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