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參數(shù)資料
| 型號： | PC28F640J3F75A |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, PBGA64 |
| 封裝： | LEAD FREE, BGA-64 |
| 文件頁數(shù)： | 26/66頁 |
| 文件大?。?/td> | 740K |
| 代理商： | PC28F640J3F75A |
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Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
March 2010
32
208032-02
8.1.2
Output Disable
With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled.
Output signals DQ[15:0] are placed in a high-impedance state.
8.2
Bus Writes
Writing or Programming to the device, is where the host writes information or data into
the flash device for non-volatile storage. When the flash device is programmed, ‘ones’
are changed to ‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase
operation must be performed. Writing commands to the Command User Interface (CUI)
enables various modes of operation, including the following:
Reading of array data
Common Flash Interface (CFI) data
Identifier codes, inspection, and clearing of the Status Register
Block Erasure, Program, and Lock-bit Configuration (when VPEN = VPENH)
Erasing is performed on a block basis – all flash cells within a block are erased together.
Any information or data previously stored in the block will be lost. Erasing is typically
done prior to programming. The Block Erase command requires appropriate command
data and an address within the block to be erased. The Byte/Word Program command
requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear
Block Lock-Bits command requires the command and address within the device to be
cleared.
The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or CEX (CEX low is defined as the combination of pins
CE0, CE1, and CE2 that enable the device. CEX high is defined as the combination of
pins CE0, CE1, and CE2 that disable the device. See Table 17 on page 30). Standard
microprocessor write timings are used.
Table 18: Enhanced Configuration Register
Reserved
Page
Length
Reserved
ECR
15
ECR
14
ECR
13
ECR
12
ECR
11
ECR
10
ECR
9
ECR
8
ECR
7
ECR
6
ECR
5
ECR
4
ECR
3
ECR
2
ECR
1
ECR
0
BITS
DESCRIPTION
NOTES
ECR[15:14]
RFU
All bits should be set to 0.
ECR.13
“1” = 8-Word Page mode
“0” = 8-Word Page mode (Default)
Either “1” or “0” is for 8-word sense in page
mode.
ECR[12:0]
RFU
All bits should be set to 0.
Table 19: Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command
Bus
Cycles
Required
First Bus Cycle
Second Bus Cycle
Oper
Addr(1)
Data
Oper
Addr(1)
Data
Set Enhanced Configuration
Register (Set ECR)
2
Write
ECD
0060h
Write
ECD
0004h
1. ECD = Enhanced Configuration Register Data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F640J3F75B | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel |
| PC28F640J3F75B TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 75NS TBGA |
| PC28F640J3F75D | 制造商:Micron Technology Inc 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel 制造商:Micron Technology 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) |
| PC28F640J3F75E | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays |
| PC28F640P30B85 | 制造商:Intel 功能描述:MM#873919 64MB FLASH SOLD->NUM |
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