- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299624 > PC28F640J3F75A 4M X 16 FLASH 2.7V PROM, PBGA64 PDF資料下載
參數(shù)資料
| 型號： | PC28F640J3F75A |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, PBGA64 |
| 封裝： | LEAD FREE, BGA-64 |
| 文件頁數(shù)： | 19/66頁 |
| 文件大?。?/td> | 740K |
| 代理商： | PC28F640J3F75A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
March 2010
26
208032-02
Table 12: Write Operations
#
Symbol
Parameter
Density
Valid for All
Speeds
Unit
Notes
Min
Max
W1
tPHWL (tPHEL)
RP# High Recovery to WE# (CEX) Going Low
32 Mbit
150
—
ns
1,2,3,4
64 Mbit
180
—
128 Mbit
210
—
W2
tELWL (tWLEL)CEX (WE#) Low to WE# (CEX) Going Low
All
0
—
1,2,3,5
W3
tWP
Write Pulse Width
60
—
1,2,3,5
W4
tDVWH (tDVEH)
Data Setup to WE# (CEX) Going High
50
—
1,2,3,6
W5
tAVWH (tAVEH)
Address Setup to WE# (CEX) Going High
55
—
1,2,3,6
W6
tWHEH (tEHWH)CEX (WE#) Hold from WE# (CEX) High
0
—
1,2,3
W7
tWHDX (tEHDX)
Data Hold from WE# (CEX) High
0
—
1,2,3
W8
tWHAX (tEHAX)
Address Hold from WE# (CEX) High
0
—
1,2,3
W9
tWPH
Write Pulse Width High
30
—
1,2,3,7
W11
tVPWH (tVPEH)VPEN Setup to WE# (CEX) Going High
0
—
1,2,3,4
W12
tWHGL (tEHGL)
Write Recovery before Read
35
—
1,2,3,8
W13
tWHRL (tEHRL)WE# (CEX) High to STS Going Low
—
500
1,2,3,9
W15
tQVVL
VPEN Hold from Valid SRD, STS Going High
0
—
1,2,3,4,
9,10
Notes:
1.
CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see
2.
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
3.
A write operation can be initiated and terminated with either CEX or WE#.
4.
Sampled, not 100% tested.
5.
Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
6.
Refer to
program, or lock-bit configuration.
7.
Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going
low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
8.
For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
9.
STS timings are based on STS configured in its RY/BY# default mode.
10.
VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[5:3,1]
= 0).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC612B | 64 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612B/2 | 32 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612C | 96 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612C/2 | 48 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612D | 32 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F640J3F75B | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel |
| PC28F640J3F75B TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 75NS TBGA |
| PC28F640J3F75D | 制造商:Micron Technology Inc 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel 制造商:Micron Technology 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) |
| PC28F640J3F75E | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays |
| PC28F640P30B85 | 制造商:Intel 功能描述:MM#873919 64MB FLASH SOLD->NUM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。