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| 型號： | PC28F640J3F75A |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, PBGA64 |
| 封裝： | LEAD FREE, BGA-64 |
| 文件頁數(shù)： | 24/66頁 |
| 文件大?。?/td> | 740K |
| 代理商： | PC28F640J3F75A |
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Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
March 2010
30
208032-02
8.0
Bus Interface
This section provides an overview of Bus operations. The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of
all in-system read, write, and erase operations through the system bus. All bus cycles
to or from the flash memory conform to standard microprocessor bus cycles. Table 16
summarizes the necessary states of each control signal for different modes of
operations.
Notes:
1.
See
2.
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
3.
DQ refers to DQ[7:0] when BYTE# is low and DQ[15:0] if BYTE# is high.
4.
Refer to DC characteristics. When VPEN
≤ VPENLK, memory contents can be read but not altered.
5.
X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or VOH.
6.
In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit configuration
algorithm. It is VOH (pulled up by an external pull up resistance ≈ 10k) when the WSM is not busy, in block erase suspend
mode (with programming inactive), program suspend mode, or reset power-down mode.
7.
See
Section 11.0, “Device Command Codes” on page 48 for valid DIN (user commands) during a Write
operation.
8.
Array writes are either program or erase operations.
Table 16: Bus Operations
Mode
RP#
CEx(1)
OE#(2)
WE#(2)
VPEN
DQ15:0(3)
STS
(Default
Mode)
Notes
Async., Status, Query and
Identifier Reads
VIH
Enabled
VIL
VIH
XDOUT
High Z
4,6
Output Disable
VIH
Enabled
VIH
X
High Z
—
Standby
VIH
Disabled
XX
X
High ZHigh Z
—
Reset/Power-down
VIL
XX
X
High Z
—
Command Writes
VIH
Enabled
VIH
VIL
XDIN
High Z
6,7
Array Writes
VIH
Enabled
VIH
VIL
VPENH
XVIL
5,8
Table 17: Chip Enable Truth Table for 32-, 64-, 128-Mb
CE2
CE1
CE0
DEVICE
VIL
Enabled
VIL
VIH
Disabled
VIL
VIH
VIL
Disabled
VIL
VIH
Disabled
VIH
VIL
Enabled
VIH
VIL
VIH
Enabled
VIH
VIL
Enabled
VIH
Disabled
Note:
For single-chip applications, CE2 and CE1 can be connected to VSS.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F640J3F75B | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel |
| PC28F640J3F75B TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 75NS TBGA |
| PC28F640J3F75D | 制造商:Micron Technology Inc 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel 制造商:Micron Technology 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) |
| PC28F640J3F75E | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays |
| PC28F640P30B85 | 制造商:Intel 功能描述:MM#873919 64MB FLASH SOLD->NUM |
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