- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299624 > PC28F640J3F75A 4M X 16 FLASH 2.7V PROM, PBGA64 PDF資料下載
參數(shù)資料
| 型號： | PC28F640J3F75A |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, PBGA64 |
| 封裝： | LEAD FREE, BGA-64 |
| 文件頁數(shù)： | 2/66頁 |
| 文件大小： | 740K |
| 代理商： | PC28F640J3F75A |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
March 2010
10
208032-02
The Status Register indicates when the WSM’s block erase, program, or lock-bit
configuration operation completes.
The STS (status) output gives an additional indicator of WSM activity by providing both
a hardware signal of status (versus software polling) and status masking (interrupt
masking for background block erase, for example). Status indication using STS
minimizes both CPU overhead and system power consumption. When configured in
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates
that the WSM is ready for a new command, block erase is suspended (and
programming is inactive), program is suspended, or the device is in reset/power-down
mode. Additionally, the configuration command allows the STS signal to be configured
to pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design
decoder logic typically required for multi-chip designs. External logic is not required
when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device:
BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high
byte.
BYTE#-high enables16-bit operation; address A1 becomes the lowest order
address and address A0 is not used (don’t care).
block diagram.
When the device is disabled (see Table 17, “Chip Enable Truth Table for 32-, 64-, 128-
RP# is at VIL, a further power-down mode is enabled which minimizes power
consumption and provides write protection during reset. A reset time (tPHQV) is
required from RP# going high until data outputs are valid. Likewise, the device has a
wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at
VIL, the WSM is reset and the Status Register is cleared.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC612B | 64 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612B/2 | 32 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612C | 96 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612C/2 | 48 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| PC612D | 32 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F640J3F75B | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel |
| PC28F640J3F75B TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 75NS TBGA |
| PC28F640J3F75D | 制造商:Micron Technology Inc 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel 制造商:Micron Technology 功能描述:NOR Flash Parallel 3V/3.3V 64Mbit 8M/4M x 8bit/16bit 75ns 64-Pin EBGA T/R 制造商:Micron Technology 功能描述:NUMONYX EMBEDDED FLASH MEMORY (J3 65NM) SINGLE BIT PER CELL (SBC) |
| PC28F640J3F75E | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays |
| PC28F640P30B85 | 制造商:Intel 功能描述:MM#873919 64MB FLASH SOLD->NUM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。