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參數(shù)資料
| 型號(hào)： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁(yè)數(shù)： | 69/76頁(yè) |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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DataSheet Revision 1.1
Page 69
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
Read from EPP Data Register (EPP Read Data cycle)
PCI CLK no (1
st
Transaction)
1
4
8
7-8
11
14-15
- Start of PCI Read fromEPP Data register
- Start of EPP data read cycle on parallel port side.
- PCI transaction completes with a ‘retry’ (without affecting ongoing EPP read data cycle) as EPP cycle cannot complete within 16 PCI CLK cycles
- Peripheral Asserts BUSY in response to the host driving AFD_N low.
- Host responds to BUSY by de-asserting AFD_N (3 clock cycles after sampling BUSY)
- Peripheral Deasserts BUSY
- EPP cycle completed.
PCI CLK no (Retry Transaction)
1
5
Tafd (PCI clk to valid AFD_N)
Tstb (PCI clk to valid STB_N)
Tpd (PCI clk to valid Parallel Data) - 16ns max*
EPP Read Data Cycle duration is dependant upon the timng response of the peripheral’s BUSY line and the parallel port filters.
Example waveformhas the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to
the peripheral’s BUSY line when the filters are enabled.
*These values exclude the effects of external parasitic (board) capacitances.
- Start of Retry transaction, to the original read fromEPP data register
- Retry transaction completes with “Data Transfer”, without initiating another EPP read Data cycle.
- 16ns max*
- 16ns max*
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相關(guān)代理商/技術(shù)參數(shù) |
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| OX16PCI954-TQC60-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated Quad UART and PCI interface |
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