- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383727 > OX16PCI952-TQFP-A (Electronic Theatre Controls, Inc.) Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface PDF資料下載
參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 24/76頁 |
| 文件大小： | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
Note 4 : Powerdown behaviour of the MIO pins is different when associated with function 0 or function 1. See section “Power Management”.
6.5
PCI Interrupts
DataSheet Revision 1.1
Page 24
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
Interrupts in PCI systems are level-sensitive and can be
shared. In the OX16PCI952, there are five sources of
interrupts - one fromeach UART channel, two fromMulti-
Purpose IO pins (MIO0 to MIO1), and one fromthe parallel
port.
All interrupts can be routed to the PCI interrupt pins, INTA#
or INTB#. The default values assigned to the interrupt pin
field within each functions PCI configuration space results
in all Function 0 interrupts to be made available on the
INTA# pin, and all Function1 interrupts also to be made
available on the INTA#pin (The
interrupt pin
fields are the
same).
These default interrupt pin values may be modified (for
example, to map function 1 interrupts on the INTB#line or
disable all interrupts altogether) by writing to the Interrupt
Pin field in each function’s PCI configuration Space using
the serial EEPROMfacility. The Interrupt Pin field is
normally considered a hard-wired read-only value in PCI. It
indicates to systemsoftware which PCI interrupt pin (if any)
is used by a function. The interrupt pin may only be
modified using the serial EEPROM facility, and card
developers must not set any value which violates the PCI
local bus specification on this issue. If in doubt, the default
values should be used.
Table 7
relates the Interrupt Pin field to the device pin
used.
Interrupt Pin Field Value
1
0
1
2
3 to 255
Table 7: ‘Interrupt pin’ definition
NOTE 1:
The OXPCI952 has only 2 interrupt pins : INTA#and INTB# Interrupt Pin
values other than 1 or 2, will result in that function not being able to assert
an interrupt.
During the systeminitialisation process and PCI device
configuration, systemspecific software reads the interrupt
pin field to determne which (if any) interrupt pin is used by
each function. It programmes the systeminterrupt router to
logically connect this PCI interrupt pin to a systemspecific
interrupt vector (IRQ). It then writes this routing information
Interrupt Pin used
None
INTA#
INTB#
Reserved
to the Interrupt Line field in the functions PCI configuration
space. Device driver software must then hook the interrupt
using the information in the Interrupt Line field.
The Interrupt status for all sources of interrupts are
available using the GIS register in the Local Configuration
Register set, which can be accessed using I/O or Memory
accesses fromboth logical functions. This facility enables
each function to snoop on interrupts asserted fromthe
other function regardless of the interrupt routing.
This is
valid only when the device is operating in the dual-function
mode.
The 5 sources of interrupts on the OX16PCI952, can be
enabled/disabled individually using the options in the local
configuration register “GIS”.
By default, the interrupt options for the UARTs and the
parallel port are enabled in the GIS register. Following the
initial PCI configuration process, any UART based
interrupts that are generated as a result of 1
st
enabling
interrupts in the UART’s interrupt register (the ISR register)
will result in the assertion of the UART interrupt on the
interrupt pin of function 0. By the same token, any parallel
port based interrupts will result in the assertion of the
parallel port interrupt on the interrupt pin of function 1.
Once the interrupt options for the Multi-purpose MIO pins
(MIO0, MIO1) are enabled in the GIS register, the assertion
of these pins will, following the initial PCI configuration
process, assert an interrupt on the selected functions
interrupt pin. The sense of the MIO pin (active-high or
active-low) that generates an interrupt is controlled by the
options in the MIC register.
For greater flexibility, the MIO pins can be individually
associated with either function0 or function1, thereby
affecting the selected functions interrupt, power-down, or
power management event logic.
Once an interrupt has been asserted, this interrupt can only
be removed by the device driver either by disabling the
relevant controls in the GIS register or by removing the
conditions on the 5 interrupt sources. For the UARTs, this
will require reads of the relevant register to clear any UART
based interrupts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OX16PCI954 | Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A | Integrated Quad UART and PCI interface |
| OX4240 | OCXO |
| OX1040 | OCXO |
| OX1041 | OCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX16PCI954 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954_05 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954-TQA1G | 功能描述:外圍驅(qū)動器與原件 - PCI PCI bridge to quad serial & para. port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| OX16PCI954-TQC60-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A1 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。