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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 18/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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DataSheet Revision 1.1
Page 18
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
6.3.2
IO space
When the dual-mode of the device is utilised, then BAR 0
and BAR 1 of function 1 are used to access the internal
Parallel Port through I/O transactions.
Memory accesses to
the parallel port are not possible.
These I/O BARs correspond to the two sets of registers
defined to operate an IEEE1284 EPP and bi-directional
Parallel Port. BAR0 reserves an 8-byte block of I/O space
and BAR1 reserves a 4 byte-block of I/O space.
Once the I/O access enable bits in the Command register
(of this functions PCI configuration space) are set, the
internal parallel port can be accessed using the mappings
shown in the following table.
See section “Bi-Directional
Parallel Port” for more details.
Register
Name
PDR
ecpAFifo
DSR
(EPP mode)
(Other modes)
DCR
EPPA
EPPD1
EPPD2
EPPD3
EPPD4
Register
Name
EcpDFifo
TFifo
CnfgA
CnfgB
ECR
-
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example:
BAR0 = 0x00000379 (8 bytes of I/O at address 0x378)
BAR1 = 0x00000779 (4 bytes of I/O at address 0x778)
If this relationship is not used, customdrivers will be
needed.
PCI access to parallel port
BAR 0 I/O Address Offset,
in Function 1
000h
000h
001h
001h
002h
003h
004h
005h
006h
007h
BAR1 I/O Address Offset,
in Function 1
400h
400h
400h
401h
402h
403h
.
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