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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 53/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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8.1.4
To use the Extended Capabilities Port (‘ECP’) mode, the
mode field of the Extended Control Register (ECR[7:5])
must be set to ‘011’ using the negotiation steps as defined
by the IEEE1284 specification.
ECP mode is compatible with the Microsoft
register
definition for ECP, and the IEEE-1284 bus protocol and
timng.
The ECP mode supports the decompression of
Run-length
encoded
(RLE) data, in hardware. The RLE received data
is expanded automatically by the correct number, into the
ECP receiver FIFO.
Run-length encoding
on data to be
transmtted is not available in hardware. This needs to be
handled in software, if this feature is required.
Assumng that the upper block is located 400h above the
lower block, the ECP registers are found at offset 000-007h
and 400-402h.
DataSheet Revision 1.1
Page 53
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
ECP mode
8.2
Parallel port interrupt
The parallel port interrupt is asserted on function 1’s
interrupt pin (INTA#by default, on the OX16PCI952). This
interrupt is enabled by setting bit 4 of the DCR register.
When the interrupt is enabled, a rising edge of the ACK#
(INTR#) pin results in a parallel port interrupt to be
asserted on function 1’s interrupt pin and this interrupt state
to be mrrored in the register DSR, bit 2. This condition is
maintained until the status register (DSR) is read, which
clears the interrupt and clears the interrupt status field in
this register (DSR[2]).
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