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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 54/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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DataSheet Revision 1.1
Page 54
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
8.3
Register Description
The parallel port registers are described below.
It is assumed that the upper block is placed 400h above the lower block.
Register
Name
Offset
Address
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPP (Compatibility Mode) Registers
PDR
ecpAFifo
DSR
(EPP mode)
(Other modes)
DCR
EPPA
1
EPPD1
1
EPPD2
1
EPPD3
1
EPPD4
1
000h
000h
001h
R/W
R/W
R
Parallel Port Data Register
ECP FIFO : Address / RLE
SLCT
nBUSY
ACK#
PE
ERR#
INT#
1
Timeout
001h
002h
003h
004h
005h
006h
007h
R
nBUSY
0
ACK#
0
PE
DIR
SLCT
INT_EN
EPP Address Register
EPP Data 1 Register
EPP Data 2 Register
EPP Data 3 Register
EPP Data 4 Register
ERR#
nSLIN#
INT#
INIT#
1
1
R/W
R/W
R/W
R/W
R/W
R/W
nAFD#
nSTB#
Lower Address Block (BAR0)
Upper Address Block (BAR1)
EcpDFifo
TFifo
CnfgA
CnfgB
ECR
-
400h
400h
400h
401h
402h
403h
R/W
R/W
R
R
R/W
-
ECP Data FIFO
Test FIFO
Configuration A Register – always 90h
0
int
‘000000’
Mode[2:0]
Must write ‘00001’
Reserved
Table 25: Parallel port register set
Note 1 : These registers are only available in EPP mode.
Note 2 : Prefix ‘n denotes that a signal is inverted at the connector. Suffix ‘# denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determnable (i.e. 0xXX).
The reset value of DSR is ‘XXXXX111’.
DCR and ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
8.3.1
Parallel port data register ‘PDR’
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 (SPP mode) will drive data onto the parallel
port data lines. In all the other modes, the drivers may be
tri-stated by setting the direction bit in the DCR. Reads
fromthis register return the actual logic values on the
parallel port data lines.
8.3.2
ECP FIFO Address / RLE
A data byte written to this address will be interpreted as an
address if bit(7) is set, otherwise an RLE count for the next
data byte. Count = bit(6:0) + 1.
8.3.3
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
fromthe peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 8.1.3)
DSR[0]:
EPP mode only: Timeout
logic 0
EPP Timer Timeout has not occurred.
logic 1
EPP Timer Timeout has occurred (Reading this
bit clears it).
Other Parallel Port modes: Unused
This bit returns a ‘1’.
Device status register ‘DSR’
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