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| 型號(hào)： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁(yè)數(shù)： | 51/76頁(yè) |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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7.11.12 Good-data status register ‘GDS’
The GDS register is located at offset 0x10 of the ICR
For the definition of Good-data status refer to section 6.4.3
GDS[0]: Good Data Status
GDS[7:1]: Reserved
7.11.13 DMA Status Register ‘DMS’
The DMS register is located at offset 0x11 of the ICR. This
allows the internal TXRDY# and RXRDY# lines to be
permanently deasserted, and the current internal status to
be monitored. This mainly has applications for testing.
DMS[0]: RxRdy Status
Read Only: set when RxRdy is asserted (pin driven low).
DMS[1]: TxRdy Status
Read Only: set when TxRdy is asserted (pin driven low).
DMS[5:2] Reserved
DMS[6]: Force RxRdy Inactive
logic 0
RxRdy#acts normally
logic 1
RxRdy# is permanently inactive (high)
regardless of FIFO thresholds
DataSheet Revision 1.1
Page 51
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
DMA[7]: Force TxRdy Inactive
logic 0
TxRdy#acts normally
logic 1
TxRdy# is permanently inactive (high)
regardless of FIFO thresholds.
7.11.14 Port Index Register ‘PIX’
The PIX register is located at offset 0x12 of the ICR. This
read-only register gives the UART index. For a single
channel device such as the OX16C950 this reads ‘0’.
7.11.15 Clock Alteration Register ‘CKA’
The CKA register is located at offset 0x13 of the ICR. This
register adds additional clock control mainly for
isochronous and embedded applications. The register is
effectively an enhancement to the CKS register.
This register is cleared to 0x00 after a hardware reset to
maintain compatibility with 16C550, but is unaffected by
software reset. This allows the user to select a clock mode
and then reset the channel to work-around any timng
glitches.
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