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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 36/76頁 |
| 文件大小： | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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950 mode:
Setting ACR[5]=1 enables 950-mode trigger levels set
using the TTL register (see section 7.11.4), FCR[5:4] are
ignored.
RHR trigger levels
FCR[7:6]: Compatible Trigger levels
450, 550, extended 550, 650 and 750 modes:
The receiver FIFO trigger levels are defined using
FCR[7:6]. The interrupt trigger level and upper flow control
trigger level where appropriate are defined by L1 in the
table below. L2 defines the lower flow control trigger level.
Separate upper and lower flow control trigger levels
introduce a hysteresis element in in-band and outof-band
flow control (see section 7.9). In Byte mode (450 mode) the
trigger levels are all set to 1.
7.5
Line Control & Status
DataSheet Revision 1.1
Page 36
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
950 mode:
In simlar fashion to for transmtter trigger levels, setting
ACR[5]=1 enables 950-mode receiver trigger levels.
FCR[7:6] are ignored.
FCR
[7:6]
Mode
550
FIFO Size 16
L1
1
4
8
14
Ext. 550 / 750
FIFO Size 128
L1
1
32
64
112
650
FIFO Size 128
L1
16
32
112
120
L2
n/a
n/a
n/a
n/a
L2
1
1
1
1
L2
1
16
32
112
00
01
10
11
Table 15: Compatible Receiver Trigger Levels
A receiver data interrupt will be generated (if enabled) if the
Receiver FIFO Level (‘RFL’) reaches the upper trigger
level.
7.5.1
On the falling edge of a start bit, the receiver will wait for
1/2 bit and re-synchronise the receiver’s sampling clock
onto the centre of the start bit. The start bit is valid if the
SIN line is still low at this md-bit sample and the receiver
will proceed to read in a data character. Verifying the start
bit prevents noise generating spurious character
generation. Once the first stop bit has been sampled, the
received data is transferred to the RHR and the receiver
will then wait for a low transition on SIN (signifying the next
start bit).
The receiver will continue receiving data even if the RHR is
full or the receiver has been disabled (see section 7.11.3)
in order to maintain framng synchronisation. The only
difference is that the received data does not gettransferred
to the RHR.
7.5.2
Line Control Register ‘LCR’
The LCR specifies the data format that is common to both
transmtter and receiver. Writing 0xBF to LCR enables
access to the EFR, XON1, XOFF1, XON2 and XOFF2,
DLL and DLM registers. This value (0xBF) corresponds to
an unused data format. Writing the value 0xBF to LCR will
set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmtter and receiver data is not
False Start Bit Detection
affected. Write the desired LCR value to exit fromthis
selection.
LCR[1:0]: Data length
LCR[1:0] Determnes the data length of serial characters.
Note however, that these values are ignored in 9bit data
framng mode, i.e. when NMR[0] is set.
LCR[1:0]
00
01
10
11
Data length
5 bits
6 bits
7 bits
8 bits
Table 16: LCR Data Length Configuration
LCR[2]: Number of stop bits
LCR[2] defines the number of stop bits per serial character.
LCR[2]
Data length
No. stop
bits
1
1.5
2
0
1
1
5,6,7,8
5
6,7,8
Table 17: LCR Stop Bit Number Configuration
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