參數資料
型號: OX16PCI952-TQFP-A
廠商: Electronic Theatre Controls, Inc.
英文描述: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
中文描述: 集成高性能的雙UART,并行端口和5.0V PCI接口
文件頁數: 20/76頁
文件大小: 1386K
代理商: OX16PCI952-TQFP-A
DataSheet Revision 1.1
Page 20
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
Bits
29
Description
Reload configuration from EEPROM
.
Writing a 1 to this bit re-loads the configuration fromEEPROM. This bit is
selfclearing after an EEPROM read
Reserved
Reserved
Read/Write
EEPROM
-
Reset
0
PCI
W
30
31
-
-
-
R
0
0
6.4.2
This register configures the operation of the multi-purpose I/O pins ‘MIO[1:0]’ as follows.
Bits
Description
1:0
MIO0 Configuration Register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
3:2
MIO1 Configuration Register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
4
MIO0 Power Management Event (PME) Enable
.
A value of ‘1’ enables the MIO0 pin to set the PME_Status bit in the
Power Management Register PMCSR of the selected function, and
hence assert the PME# pin if this option has been enabled. A value of ‘0’
prevents MIO0 fromsetting the PCI PME_Status bit.
This pin can affect function 0 or function 1, through the control defined in
the GIS (local configuration) register.
5
MIO1 Power Management Event (PME) Enable
.
A value of ‘1’ enables the MIO1 pin to set the PME_Status bit in the
Power Management Register PMCSR of the selected function, and
hence assert the PME# pin if this option has been enabled. A value of ‘0’
prevents MIO1 fromsetting the PCI PME_Status bit.
This pin can affect function 0 or functon 1, through the control defined in
the GIS (local configuration) register.
31:6
Reserved
Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
Read/Write
EEPROM
W
Reset
00
PCI
RW
W
RW
00
W
RW
0
W
RW
0
-
R
0000h
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