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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 23/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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DataSheet Revision 1.1
Page 23
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
21
MIO 1 Power-down Mask
.
When set (=1) this bit enables the MIO 1 pin to issue a powerdown event by
setting the selected functions power-down sticky bit (GIS, bits 22 or 23).
The function whose powerdown sticky bit is affected is controlled by GIS, bit
27.
Note that if the MIO 1 pin is routed to Function 0, then the pin uses the UART
power-down filtering algorithm Both the UARTs and the MIO 1 pin must
indicate a power-down for the filter period before any powerdown requests are
issued, for function 0. However, when the MIO 1 pin is routed to Function 1,
then a powerdown state on the pin MIO 1 will immediately issue a powerdown
request, for function 1, without any filters.
Function 0 Powerdown interrupt Status.
This is a sticky bit. When set, it indicates a power-down request issued by
Function0. Normally this would have asserted a PCI interrupt on Function 0’s
interrupt pin (INTA#by default) if GIS bit24 were set.
This bit is cleared on reading.
Function 1 Powerdown interrupt Status.
This is a sticky bit. When set, it indicates a power-down request issued by
Function1. Normally this would have asserted a PCI interrupt on Function 1’s
interrupt pin (INTA#by default) if GIS bit25 were set.
This bit is cleared on reading.
Function0 Power-down interrupt mask
.
When set (=1), this enables Function 0 powerdown requests to assert a PCI
interrupt, on Function 0’s interrupt pin (INTA#by default)
Function1 Power-down interrupt mask
.
When set (=1), this enables Function 1 powerdown requests to assert a PCI
interrupt, on Function 1’s interrupt pin (INTA#by default)
MIO0 Function selection
.
When reset (=0), all functional and powerdown interrupt requests, and Power
Management Events (PME) due to the MIO0 pin will affect function 0.
When set ‘1’, these requests and events will affect function1.
4
MIO1 Function selection
.
When reset (=0), all functional and powerdown interrupt requests, and Power
Management Events (PME) due to the MIO1 pin will affect function 0.
When set ‘1’, these requests and events will affect function1.
4
Parallel Port Interrupt Status
.
When set (=’1’), an internal parallel port interrupt is present. This would have
issued a PCI interrupt on Function 1’s interrupt pin (INTA# by default) if GIS,
bit 29 was set.
When reset (=0), no internal parallel port interrupts are present.
Parallel Port Interrupt Enable
.
When set (=1), an internal parallel port interrupt will assert a PCI interrupt on
Function 1’s interrupt pin (INTA# by default). When reset (=0), the parallel port
will not be able to issue a PCI interrupt.
Reserved
W
RW
0
22
-
R
0
23
-
R
0
24
W
RW
0
25
W
RW
0
26
W
RW
1
27
W
RW
1
28
-
R
0
29
W
RW
1
31:30
-
R
0h
Note 1:
Note 2:
‘MIC’ (offset 0x04). As the internal MIO can assert a PCI interrupt, the inversion feature can define each external interrupt to be defined as activelow or active-
high, as controlled by the MIC register.
Note 3:
The UART Interrupt Mask register bits are all set after a hardware reset to enable the interrupt fromall internal UARTs. This will cater for generic
device-driver software that does not access the Local Configuration Registers. The default settings for UART Interrupt Mask bits can be changed using the serial
EEPROM Note that even though the UART interrupts are enabled in this register, by default after a reset the IER registers of the individual UARTs are disabled
so a PCI interrupt will not be asserted by any UART after a hardware reset.
GIS[1:0] are the inverse of UIS[6] and UIS[0] respectively.
The returned value is either the direct state of the corresponding MIO pin or its inverse as configured by the Multi-purpose I/O Configuration register
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