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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 55/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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DSR[1]: Unused
This bit returns a ‘1’.
DSR[2]: INT#
logic 0
A parallel port interrupt is pending.
logic 1
No parallel port interrupt is pending.
This bit is activated (set low) on a rising edge of the ACK#
pin. It is de-activated (set high) after reading the DSR.
DSR[3]: ERR#
logic 0
The ERR# input is low.
logic 1
The ERR# input is high.
DSR[4]: SLCT
logic 0
The SLCT input is low.
logic 1
The SLCT input is high.
DSR[5]: PE
logic 0
The PE input is low.
logic 1
The PE input is high.
DSR[6]: ACK#
logic 0
The ACK#input is low.
logic 1
The ACK#input is high.
DSR[7]: nBUSY
logic 0
The BUSY input is high.
logic 1
The BUSY input is low.
8.3.4
Device control register ‘DCR’
DCR is located at offset 002h in the lower block. It is a
read-write register which controls the state of the peripheral
inputs and enables the peripheral interrupt. When reading
this register, bits 0 to 3 reflect the actual state of the STB#
AFD#, INIT#and SLIN#pins, respectively.
When in the EPP mode, the WRITE# DATASTB#and the
ADDRSTB#pins are normally controlled by the EPP
controller, for EPP bus signalling, but writes to the
corresponding bits in the DCR register will override the
EPP controllers states for these lines. The bits in the DCR
register must result in these lines to be in the inactive state,
allowing the EPP controller to control these lines. This is
also applicable for the ECP mode, to allow the ECP
controller to control the parallel port pins.
DCR[0]: nSTB#
logic 0
Set STB#output to high (inactive).
logic 1
Set STB#output to low (active).
During an EPP address or data cycle the WRITE#pin is
driven by the EPP controller, otherwise it is inactive.
DataSheet Revision 1.1
Page 55
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
DCR[1]: nAFD#
logic 0
Set AFD#output to high (inactive).
logic 1
Set AFD#output to low (active).
During an EPP address or data cycle the DATASTB# pin is
driven by the EPP controller, otherwise it is inactive.
DCR[2]: INIT#
logic 0
Set INIT# output to low (active).
logic 1
Set INIT# output to high (inactive).
DCR[3]: nSLIN#
logic 0
Set SLIN#output to high (inactive).
logic 1
Set SLIN#output to low (active).
During an EPP address or data cycle the ADDRSTB# pin is
driven by the EPP controller, otherwise it is inactive.
DCR[4]: ACK Interrupt Enable
logic 0
ACK interrupt is disabled.
logic 1
ACK interrupt is enabled.
DCR[5]: DIR (DIRECTION) *
logic 0
PD pins in output mode.
logic 1
PD pins in input mode.
This bit is overridden during an EPP address or data cycle,
when the direction of the port is controlled by the bus
access (read/write)
*Note : Mcrosoft’s ECP Specification states that all direction changes
related to ECP mode must first be made in the PS/2 mode, for reliable
operation
.
DCR[7:6]: Reserved
These bits are reserved and drivers must not utilise the
values associated with these bits. The OX16PCI952
returns “00” for these bits, for all parallel port modes.
8.3.5
EPP address register ‘EPPA’
EPPA is located at offset 003h in lower block, and is only
used in EPP mode. A byte written to this register will be
transferred to the peripheral as an EPP address by the
hardware. A read fromthis register will transfer an address
fromthe peripheral under hardware control.
8.3.6
EPP data registers ‘EPPD1-4’
The EPPD registers are located at offset 004h-007h of the
lower block, and are only used in EPP mode. Data written
or read fromthese registers is transferred to/fromthe
peripheral under hardware control.
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