- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383727 > OX16PCI952-TQFP-A (Electronic Theatre Controls, Inc.) Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface PDF資料下載
參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 68/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當(dāng)前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
DataSheet Revision 1.1
Page 68
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
Write to EPP Data Register (EPP Write Data cycle)
PCI CLK no (1
st
Transaction)
1
5
8
7-8
11
13-14
16
- Start of PCI write to EPP Data register
- Start of EPP data write cycle on parallel port side.
- PCI transaction completes with a ‘retry’ (without affecting ongoing EPP write data cycle) as EPP cycle cannot complete within 16 PCI CLK cycles
- Peripheral Asserts BUSY
- Host responds to BUSY by de-asserting AFD_N (3 clock cycles after sampling BUSY)
- Peripheral Deasserts BUSY
- Host responds to BUSY by asserting STB_N and the parallel port data lines (2 clock cycles after sampling BUSY).
- EPP cycle completed.
PCI CLK no (Retry Transaction)
1
5
Tafd (PCI clk to valid AFD_N)
Tstb (PCI clk to valid STB_N)
Tpd (PCI clk to valid Parallel Data) - 16ns max*
EPP Write Data Cycle duration is dependant upon the timng response of the peripheral’s BUSY line and the parallel port filters.
Example waveformhas the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to
the peripheral’s BUSY line when the filters are enabled.
*These values exclude the effects of external parasitic (board) capacitances.
- Start of Retry transaction, to the original write to EPP data register
- Retry transaction completes with “Data Transfer”, without initiating another EPP write Data cycle.
- 16ns max*
- 16ns max*
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OX16PCI954 | Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A | Integrated Quad UART and PCI interface |
| OX4240 | OCXO |
| OX1040 | OCXO |
| OX1041 | OCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX16PCI954 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954_05 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954-TQA1G | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI bridge to quad serial & para. port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| OX16PCI954-TQC60-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A1 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。