- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299581 > ORLI10G3BM680-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 333000 GATES, PBGA680 PDF資料下載
參數(shù)資料
| 型號： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 9/78頁 |
| 文件大?。?/td> | 1689K |
| 代理商： | ORLI10G3BM680-DB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
Lattice Semiconductor
ORCA ORLI10G Data Sheet
17
ORLI10G Demultiplexer (Rx) Detail
The demultiplexer module converts the incoming 16 bits of data at 622 MHz/850 MHz into 128 bits of data at 78
MHz/106 MHz or 64 bits of data at 156 MHz/212 MHz and sends it to the FPGA logic. It has been implemented in
two stages; the rst stage converts each incoming bit into a byte stream and the second stage bit interleaves these
bytes into 128/64 bits, depending upon the mode of operation. The low-speed clocks are generated by this block.
These clocks are then driven back to this block from the low-speed clock tree network. Functionally, the demulti-
plexer architecture consists of three blocks: the serial to parallel conversion, the counters, and the interleaving.
The rst stage of the line interface module (demultiplexer) converts each incoming bit of data into a byte stream on
a divided-by-8 clock. The data is rst registered on the rising edge of the clock input. The clock dividers also runs
parallel to data shift (serial to parallel) on the rising edge of the input clock. An enable is created when a complete
byte is taken in. This enable signal is used to register the serial-to-parallel converted data at the high-speed input
clock. This ensures that the data can be safely transferred to the low-speed clock. This data is then transferred to
the divided clock, allowing a timing margin of approximately half the divided clock period.
The high-speed demultiplexer converts the incoming data as blocks of bytes. The byte boundaries of incoming data
are unknown and are irrelevant to this module.
This data is then interleaved to the 128/64 bits of output data, depending on the mode of operation (divide-by-
4/divide-by-8). In 10G mode, the output data is assigned the retimed 128/64 bits of data from the rst stage of line
interface registered at the input clock [0]. In 2.5G mode, the output data is assigned four concatenated 32/16 bits of
data from the rst stage of line interface registered at input clocks [0 to 3]. The interleaving is done at bit level
because the serial-to-parallel converter operates on bits of incoming data. In 10G mode, it is assumed that all the
incoming 16 bits of data are synchronized to the input clock [0]. This block also generates the clock enables used
by the output line interface (multiplexer) module for registering the data on the high-speed clock. These enables
along with the enables from other clocks are selected through the high-speed clock MUX for the output line inter-
face block.
Figure 6 shows the valid data output bits from the demultiplexer in each of the four modes (divide-by-8, 10G and
2.5G modes, and divide-by-4, 10G and 2.5G modes). Figure 7—Figure 10 show the demultiplexer input data and
clock waveforms and output clock, enable, and data waveforms for all four modes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-2BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
| ORMC615-04 | 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。