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參數(shù)資料
| 型號： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 39/78頁 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
44
Figure 30 shows a simplied, single channel view of the recieve path in divide-by-four mode. The divide-by-8 mode
timing is similar, where the slow speed clocks are 1/8th the fast clock speed. If a primary clock is used in the FPGA,
PLL_RX2 is used to align clocks across the embedded ASIC – FPGA boundary. If the secondary clock is used in
the FPGA, PLL_RX2 is not and there is a 1.0 ns to 3.5 ns clock insertion delay incurred on the secondary clocks.
The quad 2.5 G mode requires four secondary clocks to be used, one for each 2.5 G channel. The PLL_RX1 macro
is not used as it is unneeded. The PLLs in the embedded line interface can be bypassed via the PLL_BYPASS
external FPSC pin. The feedback loop shown is connected up automatically by the design kit software. The Mode
select on the clock multiplexer in the embedded line interface is also connected up automatically by the design kit
software. If in 10G mode, one clock is used and corresponds to the RX_CLK_IN[0] external device pin.
Figure 30. Single-Channel Rx Divide-by-4 Diagram (-1 Speed Grade)
Quad 2.5G or
Single 10G
Mode
RX_DAT_IN
[3:0][P/N]
Secondary
FPGA Clock
1.0 ns
to 3.5 ns
4
Unused
161 MHz
644 MHz
RX_DAT_IN[15:0]
3ns
data
Core Clock
Trees
Primary
FPGA Clock
Tree
High Speed
Low Speed
Demultiplexer Block
Clock
Divider
/4
PLL_RX2
Q
D
PLL_RX1
RX2_VCOP
RX_CLK_IN
[3:0] [P/N]
RX2_FBCKI
Embedded Line Interface Core
FPGA
D
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
| ORMC615-04 | 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW |
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