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| 型號(hào)： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 44/78頁 |
| 文件大?。?/td> | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
49
Pin Information (continued)
Table 15. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins
M[3:0]
I
During powerup and initialization, M0—M3 are used to select the conguration mode with their val-
ues latched on the rising edge of INIT. During conguration, a pull-up is enabled.
I/O After conguration, these pins are user-programmable I/O.*
PLL_CK[0:7][TC]
I
Semidedicated PLL clock pins. During conguration they are 3-stated with a pull-up.
I/O These pins are user-programmable I/O pins if not used by PLLs after conguration.
P[TBLR]CLK[1:0][T
C]
I
Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing.
I/O After conguration, these pins are user-programmable I/O, if not used for clock inputs.
TDI, TCK, TMS
I
If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary-scan is not selected, all boundary-scan functions are inhibited once conguration is com-
plete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during congu-
ration. Each pin has a pull-up enabled during conguration.
I/O After conguration, these pins are user-programmable I/O if boundary scan is not used.*
RDY/BUSY/RCLK
O
During conguration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
During the master parallel conguration mode, RCLK is a read output signal to an external memory.
This output is not normally used.
I/O After conguration, this pin is a user-programmable I/O pin.*
HDC
O
High during conguration is output high until conguration is complete. It is used as a control output,
indicating that conguration is not complete.
I/O After conguration, this pin is a user-programmable I/O pin.*
LDC
O
Low during conguration is output low until conguration is complete. It is used as a control output,
indicating that conguration is not complete.
I/O After conguration, this pin is a user-programmable I/O pin.*
INIT
I/O
INIT
is a bidirectional signal before and during conguration. During conguration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT
is held low during power stabilization and internal clearing of memory. As an active-low input, INIT
holds the FPGA in the wait-state before the start of conguration.
After conguration, this pin is a user-programmable I/O pin.*
CS0, CS1
I
CS0
and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor congu-
ration modes. The FPGA is selected when CS0 is low and CS1 is high. During conguration, a pull-
up is enabled.
I/O After conguration, if MPI is not used, these pins are user-programmable I/O pins.*
RD/MPI_STRB
I
RD
is used in the asynchronous peripheral conguration mode. A low on RD changes D[7:3] into a
status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides.
This pin is also used as the
MPI data transfer strobe. As a status indication, a high indicates ready,
and a low indicates busy.
I/O After conguration, if the
MPI is not used, this pin is a user-programmable I/O pin.*
* The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all
other conguration pins (and the activation of all user I/Os) is controlled by a second set of options.
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