參數(shù)資料
型號(hào)： ORLI10G3BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 25/78頁(yè)
文件大?。?/td> 1689K
代理商： ORLI10G3BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
31
Typically, the following reset sequence should be followed for the ORLI10G:
Place the device in reset by driving RESET_TX = 1 and RESET_RX = 1 (or FPGA_RESET signal = 1), and by
placing the FPGA portion into reset.
Release the embedded core from reset by driving RESET_TX = 0 and RESET_RX = 0 and FPGA_RESET
signal = 0).
Release the FPGA portion from reset.
Line Interface Circuit Specications
Power Supply Decoupling LC Circuit
The 622 MHz—850 MHz line interface macro contains both analog and digital circuitry. The line interface function,
for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop
to provide its divided clocks. The internal analog phase-locked loop contains a voltage-controlled oscillator. This cir-
cuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic
gates and parasitic inductive elements. Generated noise that contains frequency components beyond the band-
width of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will
impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit ele-
ments.
Additional power supply ltering in the form of an LC π lter section will be used between the power supply source
and these device pins as shown in Figure 17. The corner frequency of the LC lter is chosen based on the power
supply switching frequency, which is between 100 kHz and 300 kHz in most applications.
Capacitor C1 is a large electrolytic capacitor to provide the basic cut-off frequency of the LC lter. For example, the
cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capacitors C2 and C3
are smaller ceramic capacitors designed to provide a low-impedance path for a wide range of high-frequency sig-
nals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the
device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended lter for
the HSI macro is shown below: L= 4.7 H, RL = 1, C1 = 4.7 F, C2 = 0.01 F, C3 = 0.01 F.
Figure 17. Sample Power Supply Filter Network for Analog LI Power Supply Pins
C2
+
C3
+
TO DEVICE
VDDA_[7:4]
VSSA_[7:4]
C1
+
FROM POWER
SUPPLY SOURCE
L
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參數(shù)描述
ORLI10G-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G5-FPSC-EV 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓:
ORM0200-03600 N-70 制造商:SMC Corporation of America 功能描述:O-RING
ORM120A110 制造商:Ssac 功能描述:
ORMC615-04 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW
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