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參數(shù)資料
| 型號(hào)： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 45/78頁 |
| 文件大?。?/td> | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
5
Description
FPSC Denition
FPSCs, or Field-Programmable System Chips, are devices that combine eld-programmable logic with ASIC, or
mask-programmed logic, on a single device. FPSCs provide the time to market and the exibility of FPGAs, the
design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of
ASICs.
FPSC Overview
Lattice's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of
programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efciency, none of the
FPGA functionality is changed; all of the Series 4 FPGA capability is retained: embedded block RAMs, MPI, PCMs,
boundary scan, etc. Columns of programmable logic are replaced on one side of the device, allowing pins from the
replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain their
FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
area efcient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to provide a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the ispLEVER Development System.
Series 4-based FPSCs expand this interface by providing a link between the embedded block and the multimaster
32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic func-
tions, including the embedded block RAMs and the microprocessor interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system exibility, FPGA conguration RAMs are available for use by the embedded core. This
supports user-programmable options in the embedded core, in turn allowing greater exibility. Multiple embedded
core congurations may be designed into a single device with user-programmable control over which congura-
tions are implemented, as well as the capability to change core functionality simply by reconguring the device.
ispLEVER Development System
The ispLEVER development system is used to process a design from a netlist to a congured FPGA. This system
is used to map a design onto the ORCA architecture and then place and route it using ispLEVER's timing-driven
tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design
entry, synthesis, simulation, and timing analysis.
The ispLEVER development system interfaces to front-end design entry tools and provides the tools to produce a
congured FPGA. In the design ow, the user denes the functionality of the FPGA at two points in the design ow,
the design entry and the bit stream generation stage. Recent improvements in ispLEVER allow the user to provide
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PDF描述 |
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| ORT82G5-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-2BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
| ORMC615-04 | 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW |
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