參數(shù)資料
型號： ORLI10G3BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 49/78頁
文件大小： 1689K
代理商： ORLI10G3BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
53
Pin Information (continued)
In Table 17, an output refers to a signal owing into the FGPA logic (out of the embedded core) and an input refers
to a signal owing out of the FPGA logic (into the embedded core).
Table 17. Embedded Core/FPGA Interface Signal Description
Symbol
I/O
Description
Receive Signals
RX_DAT_OUT<127:0>
O
Data from demultiplexer on receive side.
RX_CLK8_OUT<3:0>
O
Divided down clocks on receive side.
RX_ENB8_OUT<3:0>
O
Data enables on receive side.
RX1_VCOP
O
RX1_PLL output clock on receive side (M/N clock) after phase select.
RX1_VCO
O
RX1_PLL output clock on receive side (M/N clock) before phase select.
RX2_VCOP
O
RX2_PLL output clock on receive side (x1 clock) before phase select.
RX2_VCO
O
RX2_PLL output clock on receive side (x1 clock) before phase select.
RX2_FBCKI
I
PLL feedback input to RX2_PLL. This allows for the removal of the FPGA clock
routing delay.
RX1_BYPASS
I
Set to 1 to bypass the RX1 PLL.
RX2_BYPASS
I
Set to 1 to bypass the RX2 PLL
RX_LOCK
O
Lock the signal for RX1_PLL and RX2_PLL. This signal is a logical OR of the
lock signal from both PLLs. It is not integrated; thus, small glitches can occur
on this signal during normal PLL operation.
Transmit Signals
TX_DAT_IN<127:0>
I
Data to multiplexer on transmit side.
TX_CLK8_IN<3:0>
I
Clocks to multiplexer on transmit side.
TX_ENB8_IN<3:0>
I
Data enables on transmit side.
TX1_VCOP
O
TX1_PLL output clock on transmit side (M/N clock) after phase select.
TX1_VCO
O
TX1_PLL output clock on transmit side (M/N clock) before phase select.
TX2_VCOP
O
TX2_PLL output clock on transmit side (x1 clock) after phase select.
TX2_VCO
O
TX2_PLL output clock on transmit side (x1 clock) before phase select.
TX2_FBCKI
I
PLL feedback input to TX2 PLL. This allows for the removal of the FPGA clock
routing delay.
TX1_BYPASS
I
Set to 1 to bypass the TX1 PLL.
TX2_BYPASS
I
Set to 1 to bypass the TX2 PLL.
TX_LOCK
O
Lock signal for TX1_PLL and TX2_PLL. This signal is a logical OR of the lock
signal from both PLLs. It is not integrated; thus, small glitches can occur on
this signal during normal operation.
VSS_A<7:4>
—
Analog ground for the embedded line interface PLLs.
VDD33_A<7:4>
—
Analog power supply for the embedded line interface PLLs.
Miscellaneous Signals
FPGA_RESET
I
A logic 1 resets all receive and transmit logic, including PLLs.
相關(guān)PDF資料
PDF描述
ORT82G5-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORT82G5-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
OS10040280G-012 FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-10-X-9-M-3-05-FA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G5-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORM0200-03600 N-70 制造商:SMC Corporation of America 功能描述:O-RING
ORM120A110 制造商:Ssac 功能描述:
ORMC615-04 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*