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參數(shù)資料
| 型號： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 35/78頁 |
| 文件大?。?/td> | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
40
LVDS Buffer Characteristics
Termination Resistor
The LVDS drivers and receivers operate on a 100 differential impedance, as shown below. External resistors are
not required. The differential driver and receiver buffers include termination resistors inside the device package, as
shown in Figure 24.
Figure 24. LVDS Driver and Receiver and Associated Internal Components
LVDS Driver Buffer Capabilities
Under worst-case operating condition, the LVDS driver must withstand a disabled or unpowered receiver for an
unlimited period of time without being damaged. Similarly, when its outputs are short-circuited to each other or to
ground, the LVDS driver will not suffer permanent damage. Figure 25 illustrates the terms associated with LVDS
driver and receiver pairs.
Figure 25. LVDS Driver and Receiver
Figure 26. LVDS Driver
LVDS DRIVER
50
LVDS RECEIVER
CENTER TAP
DEVICE PINS
100
EXTERNAL
VDDD = 3.3 V
~ 14 k
.01 F
VGPD
VOA
VOB
VIA
VIB
A
B
AA
BB
DRIVER
INTERCONNECT
RECEIVER
VOA
A
VOB
B
CA
CB
RLOAD
VOD = (VOA – VOB)
V
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相關(guān)代理商/技術(shù)參數(shù) |
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| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
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