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參數(shù)資料
| 型號： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 78/78頁 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
9
from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x (the input clock frequency). Each program-
mable PLL provides two outputs that have different multiplication factors but can have the same phase relation-
ships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input
buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have pro-
grammable (12.5% steps) phase differences.
Additional highly tuned and characterized Dedicated Phase-Locked Loops (DPLLs) are included to ease system
designs. These DPLLs meet ITU-T G.811 primary clocking specications and enable system designers to very
tightly target specied clock conditioning not traditionally available in the universal PPLLs. Initial DPLLs are tar-
geted to low-speed networking DS1 and E1, and also high-speed SONET/SDH networking STS-3 and STM-1 sys-
tems.
Embedded Block RAM
New 512 x 18 quad-port RAM blocks are embedded in the FPGA core to signicantly increase the amount of mem-
ory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two
byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available,
as well as direct connection to the high-speed system bus.
Additional logic has been incorporated to allow signicant exibility for FIFO, constant multiply, and two-variable
multiply functions. The user can congure FIFO blocks with exible depths of 512k, 256k, and 1k, including asyn-
chronous and synchronous modes and programmable status and error ags. Multiplier capabilities allow a multiple
of an 8-bit number with a 16-bit xed coefcient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-
bit output). On-the-y coefcient modications are available through the second read/write port. Two 16 x 8-bit
CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can
also be preloaded at device conguration time.
Conguration
The FPGAs functionality is determined by internal conguration RAM. The FPGAs internal initialization/congura-
tion circuitry loads the conguration data at powerup or under system control. The conguration data can reside
externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low, pin-count method
for conguring FPGAs.
The RAM is loaded by using one of several conguration modes. Supporting the traditional master/slave serial,
master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface
and embedded system bus to perform both programming and readback. Daisy chaining of multiple devices and
partial reconguration are also permitted.
Other conguration options include the initialization of the embedded-block RAM memories and FPSC memory as
well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE
1149.2) port is also available meeting in-system programming (ISP) standards (IEEE 1532 Draft).
Additional Information
Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPGA and FPSC
devices, or visit our website at: http://www.latticesemi.com
相關PDF資料 |
PDF描述 |
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| ORT82G5-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-2BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
| ORMC615-04 | 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW |
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