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| 型號： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 46/78頁 |
| 文件大?。?/td> | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
50
Pin Information (continued)
Table 15. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
WR/MPI_RW
I
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write transfer
to the FPGA.
I/O After conguration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.*
PPC_A[14:31]
I
During MPI mode, the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master
utilizing the least-signicant bits of the PowerPC 32-bit address.
MPI_BURST
I
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indicates
that the current transfer is not a burst.
MPI_BDIP
I
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the
second beat in front of the current one is requested by the master. Negated before the burst transfer
ends to abort the burst data phase.
MPI_TSZ[0:1]
I
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for
the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
A[21:0]
O
During master parallel mode, A[21:0] address the conguration EPROMs up to 4 Mbytes.
I/O If not used for MPI, these pins are user-programmable I/O pins after conguration.*
MPI_ACK
O
In
MPI mode, this is driven low indicating the MPI received the data on the write cycle or returned data
on a read cycle.
I/O If not used for MPI, these pins are user-programmable I/O pins after conguration.*
MPI_CLK
I
This is the PowerPC synchronous, positive-edge bus clock used for the
MPI interface. It can be a
source of the clock for the embedded system bus. If MPI is used, this will be the AMBA bus clock.
I/O If not used for MPI, these pins are user-programmable I/O pins after conguration.*
MPI_TEA
O
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal
system bus for the current transaction.
I/O If not used for MPI, these pins are user-programmable I/O pins after conguration.*
MPI_RTRY
O
This pin requests the MPC860 relinquish the bus and retry the cycle.
I/O If not used for MPI, these pins are user-programmable I/O pins after conguration.*
D[0:31]
I/O
Selectable data bus width from 8-, 16-, 32-bit in MPI mode. Driven by the bus master in a write transac-
tion and driven by MPI in a read transaction.
I
D[7:0] receive conguration data during master parallel, peripheral, and slave parallel conguration
modes when WR is low and each pin has a pull-up enabled. During serial conguration modes, D0 is
the DIN input.
O
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After conguration, if MPI is not used, the pins are user-programmable I/O pins.*
DP[0:3]
I/O
Selectable parity bus width in MPI mode from 1-, 2-, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for
D[16:23], and DP[3] for D[24:31].
After conguration, if MPI is not used, the pins are user-programmable I/O pin.*
* The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conguration
pins (and the activation of all user I/Os) is controlled by a second set of options.
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| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
| ORMC615-04 | 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW |
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