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| 型號： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 43/78頁 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
48
Pin Information
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During conguration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after conguration. The pin descriptions in Table 15 and throughout this data sheet show active-low signals with an
overscore. The package pinout tables that follow show this as a signal ending with _N. Therefore, LDC and LDC_N
are equivalent.
Table 15. Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
VDD33
—
3.3 V positive power supply. This power supply is used for 3.3 V conguration RAMs and internal
PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on
the board for proper operation.
VDD15
—
1.5 V positive power supply for internal logic.
VDDIO
—
Positive power supply used by I/O banks.
VSS
—
Ground.
PTEMP
I
Temperature sensing diode pin. Dedicated input.
RESET
I
During conguration, RESET forces the restart of conguration and a pull-up is enabled. After con-
guration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC
latches/Flip-Flops to be asynchronously set/reset.
CCLK
O
In the master and asynchronous peripheral modes, CCLK is an output which strobes conguration
data in.
I
In the slave or readback after conguration, CCLK is input synchronous with the data on DIN or
D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or
system bus modes.
DONE
I
As an input, a low level on DONE delays FPGA start-up after conguration.*
O
As an active-high, open-drain output, a high level on this signal indicates that conguration is com-
plete. DONE has an optional pull-up resistor.
PRGM
I
PRGM
is an active-low input that forces the restart of conguration and resets the boundary-scan
circuitry. This pin always has an active pull-up.
RD_CFG
I
This pin must be held high during device initialization until the INIT pin goes high. This pin always
has an active pull-up.
During conguration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states
all of the I/O.
After conguration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL func-
tion as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on
RD_CFG
will initiate readback of the conguration data, including PFU output states, starting with
frame address 0.
RD_DATA/TDO
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides conguration data
out. If used in boundary-scan, TDO is test data out.
CFG_IRQ/MPI_IR
Q
O
During JTAG, slave, master, and asynchronous peripheral conguration, assertion on this CFG_IRQ
(active-low) indicates an error or errors for block RAM or FPSC initialization.
MPI active-low interrupt
request output, when the MPI is used.
*The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all
other conguration pins (and the activation of all user I/Os) is controlled by a second set of options.
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| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
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