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參數(shù)資料
| 型號： | ORLI10G3BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 77/78頁 |
| 文件大?。?/td> | 1689K |
| 代理商： | ORLI10G3BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
8
The improved routing resources offer great exibility in moving signals to and from the logic core. This exibility
translates into an improved capability to route designs at the required speeds when the I/O signals have been
locked to specic pins.
System-Level Features
The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system
bus, quad-port embedded block RAMs, universal programmable phase-locked loops, and the addition of highly
tuned networking specic phase-locked loops. These functional blocks support easy glueless system interfacing
and the capability to adjust to varying conditions in today's high-speed networking systems.
Microprocessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-bit,
16-bit, and 32-bit interfaces with optional parity to the Motorola
PowerPC 860 bus, it can be used for conguration
and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4
embedded system bus at 66 MHz performance.
The MPI provides, following conguration, a system-level microprocessor interface through the system bus to the
user-dened logic within the FPGA, and includes access to the embedded block RAM. The MPI supports burst
data read and write transfers, allowing short, uneven transmission of data through the interface by including data
FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-
beat (16 x 1 bytes).
The 32-bit device identication code (device_id) for the ORLI10G is at system bus register address 0x0-0x3. (see
Figure 1. ORLI10G 32-bit Device Identication Code
System Bus
An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, conguration
logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA speci-
cation Rev 2.0 AHB protocol, the embedded system bus offers arbiter, decoder, master, and slave elements.
The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset func-
tions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is
integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the micro-
processor interface clock, conguration clock (for slave conguration modes), internal oscillator, user clock from
routing, or port clock (for JTAG conguration modes). In the ORLI10G FPSC, the system bus is not connected to
the embedded core.
Phase-Locked Loops
Four user PLLs are provided for ORCA Series 4 FPSCs. Programmable PLLs can be used to manipulate the fre-
quency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks
0000_000101000_1_001000_00000011101_1
First OR4E04
40 rows (OR4E04)
FPSC identifier
Series 4
Manufacturer ID
based FPSC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-2BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORT82G5-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORM0200-03600 N-70 | 制造商:SMC Corporation of America 功能描述:O-RING |
| ORM120A110 | 制造商:Ssac 功能描述: |
| ORMC615-04 | 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW |
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