參數(shù)資料
型號(hào)： ORLI10G3BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 36/78頁(yè)
文件大?。?/td> 1689K
代理商： ORLI10G3BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
41
ORLI10G Interface Timing Diagrams
This section describes the timing at the FPGA – Core boundary. There are 4 distinct timing modes available for use
with the ORLI10G device (note that for TX, 10G mode can be used for either 10G or 2.5G operation):
10G RX and TX with PLL used across the interface.
10G RX and TX with NO PLL used across the interface.
Quad 2.5G RX with NO PLL used across the interface plus 10G TX with PLL used across the interface.
Quad 2.5G RX with NO PLL used across the interface plus 10G TX with NO PLL used across the interface.
Figure 27 shows a simplied, single channel view of the transmit path in divide-by-four mode. The divide-by-8
mode timing is similar, where the slow speed clocks are 1/8th the fast clock speed. PLL_TX2 is used to align clocks
across the Embedded Line Interface – FPGA boundary. The PLL_TX1 macro is not used as it is unneeded. The
PLLs in the embedded line interface can be bypassed via the PLL_BYPASS external FPSC pin. The feedback loop
shown is connected up automatically by the design kit software.
Figure 27. Single Channel Tx Divide-by-4 Diagram (-1 Speed Grade)
161 MHz
Unused
PLL_TX2
PLL_TX1
TX2_VCOP
TX2_FBCKI
644MHz
TX_DAT_IN[15:0]
3ns
data
Core Clock
Trees
TX_DAT_OUT
[3:0][P/N]
TX_CLK_OUT
[0][P/N]
Primary
FPGA Clock
Tree
High Speed
Multiplexer Block
Clock
Divider
/4
D
Q
TX_CLK_IN[P/N]
Embedded Line Interface Core
FPGA
Q
Low Speed
相關(guān)PDF資料
PDF描述
ORT82G5-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORT82G5-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
OS10040280G-012 FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-10-X-9-M-3-05-FA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G5-FPSC-EV 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓:
ORM0200-03600 N-70 制造商:SMC Corporation of America 功能描述:O-RING
ORM120A110 制造商:Ssac 功能描述:
ORMC615-04 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW
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