參數(shù)資料
型號: OR4E10
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述: 現(xiàn)場可編程門陣列(現(xiàn)場可編程門陣列)
文件頁數(shù): 99/132頁
文件大小: 2667K
代理商: OR4E10
Lucent Technologies Inc.
99
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Ball
Bank
Pad
Function
Pair*
Differential
P29
N31
P28
N30
N29
M30
N28
M29
L31
L30
M28
L29
K31
K30
K29
J31
J30
K28
J29
H30
H29
J28
G31
G30
G29
H28
F31
F30
F29
E31
E30
E29
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
TL
PL19C
PL19D
V
DD
IO
PL18C
PL18D
PL17D
PL16C
PL16D
PL14C
PL14D
PL13C
PL13D
PL12C
PL12D
PL11C
PL11D
PL10C
PL10D
PL9C
PL9D
V
DD
IO
PL8C
PL8D
PL6C
PL6D
PL4C
PL4D
PL3C
PL3D
PL2C
PL2D
V
DD
IO
A12
A13
VREF
L4T_D1
L4C_D1
L3T_A0
L3C_A0
L2T_D0
L2C_D0
L1T_A0
L1C_A0
L24T_D0
L24C_D0
L23T_A0
L23C_A0
L22T_D1
L22C_D1
L21T_D1
L21C_D1
L20T_D0
L20C_D0
L19T_D2
L19C_D2
L18T_A0
L18C_A0
L17T_D2
L17C_D2
L16T_A0
L16C_A0
L15T_A0
L15C_A0
TRUE
COMPLEMENT
TRUE
COMPLEMENT
RDY/BUSY/RCLK
D4
VREF
A14
A15
A16
VREF
DOUT
INIT
CS1
CS0
A17
VREF
D7
LDC
HDC
D6
D5
VREF
PLL_CK0T
PLL_CK0C
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
TRUE
COMPLEMENT
Pin Information
(continued)
Table 45. OR4E6 432-Pin EBGA
(continued)
* Differential pairs and physical locations are numbered within each bank (e.g., L19C_A0 is ninteenth pair in an associated bank). The C indi-
cates complementary differential whereas a T indicates true differential. The _A0 indicates the physical location is adjacent balls in either hor-
zontal/vertical direction. Other physical indicators are as follows:
_A1 indicates one ball between pairs.
_A2 indicates two balls between pairs.
_D0 indicates balls are diagonally adjacent.
_D1 indicates diagonally adjacent separated by one physical ball.
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