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| 型號： | OR4E10 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 26/132頁 |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E10 |
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26
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Logic Cells
(continued)
The set/reset operation of the latch/FF is controlled by
two parameters: reset mode and set/reset value. When
the GSRN and local set/reset (LSR) signals are not
asserted, the latch/FF operates normally. The reset
mode is used to select a synchronous or asynchronous
LSR operation. If synchronous, LSR has the option to
be enabled only if clock enable (CE) is active or for LSR
to have priority over the clock enable input, thereby set-
ting/resetting the FF independent of the state of the
clock enable. The clock enable is supported on FFs,
not latches. It is implemented by using a 2-input multi-
plexer on the FF input, with one input being the previ-
ous state of the FF and the other input being the new
data applied to the FF. The select of this
2-input multiplexer is clock enable (CE), which selects
either the new data or the previous state. When the
clock enable is inactive, the FF output does not change
when the clock edge arrives.
The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF. An option is available to disable the
GSRN function per PFU after initial device configura-
tion.
The latch/FF can be configured to have a data front-
end select. Two data inputs are possible in the front-
end select mode, with the SEL signal used to select
which data input is used. The data input into each
latch/FF is from the output of its associated LUT,
F[7:0], or direct from DIN[7:0], bypassing the LUT. In
the front-end data select mode, both signals are avail-
able to the latches/FFs.
If either or both of these inputs is unused or is unavail-
able, the latch/FF data input can be tied to a logic 0 or
logic 1 instead (the default is logic 0).
The latches/FFs can be configured in three basic
modes:
I
Local synchronous set/reset: the input into the PFU’s
LSR port is used to synchronously set or reset each
latch/FF.
I
Local asynchronous set/reset: the input into LSR
asynchronously sets or resets each latch/FF.
I
Latch/FF with front-end select, LSR either synchro-
nous or asynchronous: the data select signal selects
the input into the latches/FFs between the LUT out-
put and direct data in.
For all three modes, each latch/FF can be indepen-
dently programmed as either set or reset. Figure 20
provides the logic functionality of the front-end select,
global set/reset, and local set/reset operations.
The ninth PFU FF, which is generally associated with
registering the carry-out signal in ripple mode func-
tions, can be used as a general-purpose FF. It is only
an FF and is not capable of being configured as a latch.
Because the ninth FF is not associated with an LUT,
there is no front-end data select. The data input to the
ninth FF is limited to the CIN input, logic 1, logic 0, or
the carry-out in ripple and half-logic modes.
5-9737(F).a
Key: C = configuration data.
Figure 20. Latch/FF Set/Reset Configurations
CE
CE
D
Q
S_SET
S_RESET
CLK
SET RESET
F
DIN
LOGIC 1
LOGIC 0
LSR
CD
GSRN
CE
CE
D
Q
CLK
SET RESET
F
DIN
LOGIC 1
LOGIC 0
CD
GSRN
LSR
CE
CE
D
Q
CLK
SET RESET
F
DIN
LOGIC 1
LOGIC 0
CD
GSRN
LSR
DIN
SEL
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