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| 型號： | OR4E10 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 47/132頁 |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E10 |
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Lucent Technologies Inc.
47
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Special Function Blocks
(continued)
Readback can be initiated at an address other than
frame 0 via the new
MPI
control registers (see the
Microprocessor
Interface section for more information).
In all cases, readback is performed at sequential
addresses from the start address.
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The
RD_CFG
input pin is also used to control
the global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
the
RD_CFG
input and readback is disabled. After con-
figuration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the
RD_CFG
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
The readback frame contains the configuration data
and the state of the internal logic. During readback, the
value of all registered PFU and PIO outputs can be
captured. The following options are allowed when
doing a capture of the PFU outputs:
I
Do not capture data (the data written to the RAMs,
usually 0, will be read back).
I
Capture data upon entering readback.
I
Capture data based upon a configurable signal inter-
nal to the FPGA. If this signal is tied to logic 0, cap-
ture RAMs are written continuously.
I
Capture data on either options two or three above.
The readback frame has an identical format to that of
the configuration data frame, which is discussed later in
the Configuration Data Format section. If LUT memory
is not used as RAM and there is no data capture, the
readback data (not just the format) will be identical to
the configuration data for the same frame. This eases a
bitwise comparison between the configuration and
readback data. The configuration header, including the
length count field, is not part of the readback frame.
The readback frame contains bits in locations not used
in the configuration. These locations need to be
masked out when comparing the configuration and
readback frames. The development system optionally
provides a readback bit stream to compare to readback
data from the FPGA. Also note that if any of the LUTs
are used as RAM and new data is written to them,
these bits will not have the same values as the original
configuration data frame either.
Global 3-State Control (TS_ALL)
To increase the testability of the ORCA Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
configuration, the TS_ALL signal is driven by the input
pad
RD_CFG
. After configuration, the TS_ALL signal
can be disabled, driven from the
RD_CFG
input pad, or
driven by a general routing signal in the upper right cor-
ner. Before configuration, TS_ALL is active-low; after
configuration, the sense of TS_ALL can be inverted.
The following occur when TS_ALL is activated:
I
All of the user I/O output buffers are 3-stated.
I
The TDO/RD_DATA output buffer is 3-stated.
I
The RD_CFG, RESET, and PRGM input buffers
remain active with a pull-up.
I
The DONE output buffer is 3-stated, and the input
buffer is pulled up.
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