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參數(shù)資料
| 型號： | OR4E10 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 36/132頁 |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E10 |
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36
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
The PIO output FF can perform output data multiplex-
ing with no PLC resources required. This type of
scheme is necessary for DDR applications which
require data clocking out of the I/O on both edges of
the clock. In this scheme, the output of OUTFF and
OUTDD are serialized and shifted out on both the posi-
tive and negative edges of the clock using the shift reg-
isters.
The PIC logic block can also generate logic functions
based on the signals on the OUTDD and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 17 is provided as a summary
of the PIO logic options.
Table 17. PIO Logic Options
Flexible I/O features allow the user to select I/O to meet
different high-speed interface requirements. These I/Os
require different input references or supply voltages.
The perimeter of the device is divided into groups of
PIOs or buffer banks. For each bank, there is a sepa-
rate V
DDIO
. Every device is equally broken up into eight
I/O banks. The V
DDIO
supplies the correct output volt-
age for a particular standard. The user must supply the
appropriate power supply to the V
DDIO
pin. Within a
bank, several I/O standards may be mixed as long as
they use a common V
DDIO
. Also, some interface stan-
dards require a specified threshold voltage known as
V
REF
. In these modes, where a particular V
REF
is
required, the device is automatically programmed to
dedicate a pin for the appropriate V
REF
which must be
supplied by the user. The V
REF
is dedicated exclusively
to the bank and cannot be intermixed with other signal-
ing requiring other V
REF
voltages. However, pins not
requiring V
REF
can be mixed in the bank. The V
REF
pad
is then no longer available to the user for general use.
See Table 14 for a list of the I/O standards supported.
Table 18. Compatible Mixed I/O Standards
0205(F).
Figure 23. ORCAHigh-Speed I/O Banks
High-Speed Memory Interfaces
PIO features allow high-speed interfaces to external
SRAM and/or DRAM devices. Series 4 I/Os provide
200 MHz ZBTrequirements when switching between
write and read cycles. ZBTallows 100% use of bus
cycles during back-to-back read/write and write/read
cycles. However, this maximum utilization of the bus
increases probability of bus contention when the inter-
faced devices attempt to drive the bus to opposite logic
values. The LVTTL I/O interfaces directly with commer-
cial ZBTSRAMs signaling and allows the versatility to
program the FPGA drive strengths from 6 mA to
24 mA.
DDR allows data to be read or written on both the rising
and the falling edge of the clock which delivers twice
the bandwidth. QDR (quad data rate) are similar, but
have separate read and write parts for over double the
bandwidth. The DDR capability in the PIO also allows
double the bandwidth per pin for generic transfer of
data between two devices. DDR doubles the memory
speed from SDRAMs without the need to increase
clock frequency. The flexibility of the PIO allows
133 MHz/266 Mbits per second performance using the
SSTL I/O features of the Series 4. All DDR interface
functions are built into the PIO.
Option
AND
Description
Output logical AND of signals
on OUTFF and clock.
Output logical NAND of signals
on OUTFF and clock.
Output logical OR of signals on
OUTFF and clock.
Output logical NOR of signals
on OUTFF and clock.
Output logical XOR of signals
on OUTFF and clock.
Output logical XNOR of signals
on OUTFF and clock.
NAND
OR
NOR
XOR
XNOR
V
DD
IO BANK
Voltage
3.3 V
Compatible Standards
LVTTL, SSTL3-I, SSTL3-II, GTL, GTL+,
PECL
LVCMOS2, SSTL2-I, SSTL2-II, LVDS,
LVPECL
LVCMOS18
HSTL I, HSTL III, HSTL IV
2.5 V
1.8 V
1.5 V
PLC ARRAY
TC
TL
TR
BC
BL
BR
C
C
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